---
title: "Emitter-bias BJT Q point and load line"
subject: "Fundamental of Electrical and Electronics Engineering"
chapter: 5
key: "semester_1/fundamental_of_electrical_and_electronics_engineering:emitter-bias-q-point"
source: https://www.bctengineer.com/q/semester_1/fundamental_of_electrical_and_electronics_engineering/emitter-bias-q-point
site: BCT Engineering
---

# Emitter-bias BJT Q point and load line

Fundamental of Electrical and Electronics Engineering · Chapter 5: Transistor

- Asked in: 2081 Baishakh (new course), 2+1+1 marks
- Video: [Transistor Biasing: What is Q-point? What is Load Line? Fixed Bias Configuration Explained](https://www.youtube.com/watch?v=5T84Jzcgj7M) — ALL ABOUT ELECTRONICS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_1/fundamental_of_electrical_and_electronics_engineering/emitter-bias-q-point
- Whole chapter: https://www.bctengineer.com/md/semester_1/fundamental_of_electrical_and_electronics_engineering/chapter-5

## Question

For the given Emitter-bias BJT network, find Q point. Draw dc load line and find region of operation. [Figure: npn BJT with β = 50; VCC = +20 V; base resistor RB = 430 kΩ from VCC to base; collector resistor RC = 2 kΩ from VCC to collector; emitter resistor RE = 1 kΩ to ground bypassed by CE = 40 µF; input vi coupled to base through 10 µF and output vo taken from collector through 10 µF.]

## Short answer

Base loop KVL: I_B = (VCC−V_BE)/[R_B+(β+1)R_E] = 19.3/481k = 40.1 µA. I_C = βI_B = 2.01 mA, V_CE = VCC−I_C R_C−I_E R_E ≈ 13.94 V. Q point: I_CQ = 2.01 mA, V_CEQ = 13.94 V. DC load line: cut‑off (20 V, 0 mA), saturation (0 V, 6.67 mA). Active region.

## Answer

For DC analysis the capacitors are open circuits; the bypass capacitor CE does not affect the DC values, so RE = 1 kΩ is in the emitter circuit. Take V_BE = 0.7 V (Si).

#### Q point

**Base loop (KVL):** VCC − I_B RB − V_BE − I_E RE = 0 with I_E = (β + 1) I_B:

```text
I_B = (VCC − V_BE)/(RB + (β + 1) RE)
    = (20 − 0.7)/(430 k + 51 × 1 k)
    = 19.3/481 k
    = 40.12 µA
I_C = β I_B = 50 × 40.12 µA = 2.006 mA
I_E = (β + 1) I_B = 2.046 mA
```

**Collector loop:**

```text
V_CE = VCC − I_C RC − I_E RE
     = 20 − 2.006 × 2 − 2.046 × 1
     = 13.94 V
```

(Taking I_E ≈ I_C: V_CE ≈ 20 − 2.006 × 3 ≈ 13.98 V.)

**Q point: I_CQ ≈ 2.01 mA, V_CEQ ≈ 13.94 V** (I_BQ ≈ 40.1 µA).

#### DC load line

Equation (I_E ≈ I_C): V_CE = VCC − I_C (RC + RE)

```text
I_C = 0       → V_CE(cutoff) = VCC = 20 V
V_CE = 0      → I_C(sat) = 20/(2 k + 1 k) = 6.67 mA

 I_C (mA)
 6.67 *
      | \
      |   \
 2.01 |- - -Q
      |      : \
      |      :   \
    0 +------:-----*----- V_CE (V)
      0    13.94   20
```

#### Region of operation

V_CE = 13.94 V is well above V_CE(sat) ≈ 0.2 V and I_C = 2.01 mA is well below I_C(sat) = 6.67 mA. The base-emitter junction is forward biased and the base-collector junction is reverse biased (V_C = 20 − 2.006 × 2 = 15.99 V > V_B = 2.75 V).

**Answer: the transistor operates in the active region**, near the middle of the load line, suitable for amplification.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In DC analysis, how are the capacitors treated?
   A. As short circuits
   B. As resistors of 40 ohm
   C. As open circuits
   D. They are removed and RE is removed too
   Answer: C. Capacitors block DC; the bypass capacitor CE does not change DC values, so RE remains. (Key point: DC analysis treatment)

2. Which formula gives I_B?
   A. (VCC - V_BE)/RB
   B. (VCC)/(RB + RC)
   C. (VCC - V_BE)/(RB + RE)
   D. (VCC - V_BE)/(RB + (beta+1) RE)
   Answer: D. The emitter current I_E = (beta+1) I_B flows through RE, so RE reflects as (beta+1) RE: 19.3/481k = 40.1 uA. (Key point: Base current formula)

3. The Q point is:
   A. I_C about 2.01 mA, V_CE about 13.94 V
   B. I_C = 6.67 mA, V_CE = 0
   C. I_C = 0, V_CE = 20 V
   D. I_C = 2.01 mA, V_CE = 20 V
   Answer: A. I_C = 50 x 40.12 uA = 2.006 mA; V_CE = 20 - 2.006x2 - 2.046x1 = 13.94 V. (Key point: Q point values)

4. The DC load line meets the axes at:
   A. V_CE = 13.94 V and I_C = 2 mA, saturation
   B. V_CE = 20 V and I_C(sat) = 6.67 mA, so Q is in the active region
   C. V_CE = 0 and I_C = 20 mA, cutoff
   D. V_CE = 20 V and I_C = 10 mA, active
   Answer: B. I_C(sat) = VCC/(RC+RE) = 6.67 mA; Q has V_CE well above 0.2 V so active. (Key point: Load line end points and region)

## Related in Fundamental of Electrical and Electronics Engineering

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