--- title: "CMOS inverter / NOT gate operation" subject: "Basic Electronics Engineering" chapter: 3 key: "semester_2/basic_electronics_engineering:cmos-inverter-operation" source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/cmos-inverter-operation site: BCT Engineering --- # CMOS inverter / NOT gate operation Basic Electronics Engineering · Chapter 3: Transistor - Asked in: 2075 Baisakh, 4 marks; 2073 Magh, 5 marks; 2069 Bhadra, 4 marks; 2067 Chaitra, 4 marks (asked 4 times) - Video: [CMOS Basics - Inverter, Transmission Gate, Dynamic and Static Power Dissipation, Latch Up](https://www.youtube.com/watch?v=CwL3ouoN7pE) — Institute of Electronics - TU Graz - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/cmos-inverter-operation - Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-3 ## Question Describe the structure and operation of the CMOS inverter (NOT gate) with necessary diagram. ## Short answer A CMOS inverter consists of a series PMOS (pull‑up) and NMOS (pull‑down) with gates tied as input. For low input, PMOS on, NMOS off, output high (VDD); for high input, NMOS on, PMOS off, output low (0 V). Static power is negligible, and output swings rail‑to‑rail. ## Answer A **CMOS inverter** (NOT gate) is built from one p-channel enhancement MOSFET (PMOS) and one n-channel enhancement MOSFET (NMOS) connected in a complementary pair. Output is the logical complement of the input. #### Structure - The two gates are tied together and form the input Vin. - The two drains are tied together and form the output Vout. - The PMOS source is connected to VDD, the NMOS source is connected to ground. ```text VDD | S --| PMOS Vin o---| G D --| +-----o Vout D --| Vin o---| G NMOS S --| | GND ``` #### Operation | Vin | PMOS | NMOS | Vout | |---|---|---|---| | 0 (low) | ON | OFF | VDD (1) | | VDD (high) | OFF | ON | 0 (0) | - **Vin = 0:** VGS(NMOS) = 0 < VT, so the NMOS is OFF. For the PMOS, VGS = −VDD, so it turns ON and connects the output to VDD. Output is high. - **Vin = VDD:** the NMOS is ON (VGS = VDD) and pulls the output to ground. The PMOS has VGS = 0 so it is OFF. Output is low. In the steady state one transistor is always OFF, so there is no direct path from VDD to ground. Static current is almost zero. #### Transfer characteristic ```text Vout VDD |----. | \ | \ (sharp transition | \ near VDD/2) 0 | '------ +----------------- Vin 0 VDD/2 VDD ``` During switching, both transistors are briefly ON, and a small current flows (dynamic power). Power consumption: P = C VDD² f. **Advantages:** very low static power, high noise margin (about 0.45 VDD), output swings fully from 0 to VDD, high packing density. It is the basis of modern digital ICs. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. When Vin = 0, which transistor is ON? A. NMOS B. Both C. PMOS, so Vout = VDD D. Neither Answer: C. PMOS has VGS = -VDD and turns on. (Key point: Vin low) 2. When Vin = VDD, what is Vout? A. VDD B. 0, since NMOS pulls it to ground C. VDD/2 D. Floating Answer: B. NMOS is ON and PMOS is OFF. (Key point: Vin high) 3. Why is static power almost zero? A. Resistors limit current B. VDD is small C. One transistor is always OFF, so no direct VDD-ground path D. The output is floating Answer: C. Complementary pair never conducts together in steady state. (Key point: Static power) 4. What is the dynamic power? A. C VDD^2 f B. VDD/R C. C VDD f^2 D. 0 Answer: A. P = C VDD² f. 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