--- title: "CMOS switch operation" subject: "Basic Electronics Engineering" chapter: 3 key: "semester_2/basic_electronics_engineering:cmos-switch" source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/cmos-switch site: BCT Engineering --- # CMOS switch operation Basic Electronics Engineering · Chapter 3: Transistor - Asked in: 2073 Bhadra, 4 marks - Video: [CMOS Basics - Inverter, Transmission Gate, Dynamic and Static Power Dissipation, Latch Up](https://www.youtube.com/watch?v=CwL3ouoN7pE) — Institute of Electronics - TU Graz - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/cmos-switch - Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-3 ## Question Explain the operation of CMOS switch with necessary diagrams. ## Short answer A CMOS transmission gate consists of a parallel NMOS and PMOS with complementary gate signals. When control is high, both transistors conduct, passing signals from 0 to VDD with low on‑resistance; when low, both are off and block the signal, eliminating threshold voltage drop. ## Answer A **CMOS switch** (transmission gate) is an electronic switch made of an NMOS and a PMOS transistor connected in parallel, with opposite gate control signals. It passes analog or digital signals in both directions with low resistance when ON, and blocks them when OFF. #### Circuit ```text +---------+ IN o---------|S NMOS D|--------o OUT | | G | | | +----|----+ | | C | | +----|----+ | +----|S PMOS D|---+ | G | +----|----+ C' (C' = inverted control) ``` The NMOS gate is driven by control C; the PMOS gate is driven by the inverse C' (through an inverter). #### Operation - **C = 1 (VDD), C' = 0:** both transistors are ON. The signal passes from IN to OUT with a low ON resistance (a few hundred ohms): **switch closed**. - **C = 0, C' = VDD:** both transistors are OFF. The path is open with very high resistance: **switch open**. #### Why both transistors? - An NMOS alone passes low voltages well but a high level is degraded (it can pass only up to VDD − VT). - A PMOS alone passes high voltages well but not low voltages. - Connected in parallel, NMOS conducts for low input levels and PMOS for high input levels, so the full range 0 to VDD is passed, with ON resistance almost constant. **Applications:** analog multiplexers, sample-and-hold circuits, analog switches in ADC/DAC, digital multiplexers, and latches. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is a CMOS switch (transmission gate) built? A. NMOS and PMOS in series with the same gate signal B. NMOS and PMOS in parallel with complementary gate signals C and C' C. Two NMOS in parallel D. One PMOS with a resistor Answer: B. The NMOS gate gets C and the PMOS gate gets the inverse C', so both turn on or off together. (Key point: Structure) 2. When C = 1 (VDD), what is the state of the switch? A. Both transistors ON, low resistance, switch closed B. Both OFF, switch open C. Only NMOS on D. Only PMOS on Answer: A. C = 1 and C' = 0 turn both devices on, passing the signal with a low ON resistance. (Key point: ON state) 3. Why are both NMOS and PMOS used? A. NMOS passes high levels poorly (only up to VDD - VT) and PMOS passes low levels poorly, so together they pass the full 0 to VDD B. To double the supply voltage C. To make the switch one-directional D. To reduce the number of control signals Answer: A. Each device covers the voltage range where the other is weak, so the whole range passes with nearly constant ON resistance. (Key point: Why both transistors) 4. When C = 0, what is the switch condition? A. Both transistors off, very high resistance, switch open B. Both on, low resistance C. NMOS on only D. Output equals VDD Answer: A. With C = 0 and C' = VDD both transistors are cut off and block the signal. (Key point: OFF state) ## Related in Basic Electronics Engineering - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Full wave bridge rectifier operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Afull-wave-bridge-rectifier) — Basic Electronics Engineering, chapter 2, asked 4× - [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6× ## Related in other subjects - [CMOS inverter operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-inverter) — Digital Logic, chapter 10 - [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2× - [CMOS characteristics; TTL 2-input AND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-ttl-and) — Digital Logic, chapter 10 - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10