---
title: "Combinational vs sequential; JK flip-flop"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:comb-vs-seq-jk"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/comb-vs-seq-jk
site: BCT Engineering
---

# Combinational vs sequential; JK flip-flop

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2070 Magh, 2+6 marks
- Video: [Comparison between Combinational and Sequential Circuits](https://www.youtube.com/watch?v=SzV4l0_1MCQ) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/comb-vs-seq-jk
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

What is the difference between combinational and sequential circuit? Discuss JK flip-flop with the help of logic diagram.

## Short answer

Combinational circuits' outputs depend only on present inputs, have no memory (e.g., ader). Sequential circuits' outputs depend on inputs and past state, use memory like flip-flops. The JK flip-flop is a clocked sequential device: J=K=0 hold, 01 reset, 10 set, 11 togle; Q(n+1)=JQ'+K'Q.

## Answer

#### Combinational versus sequential circuits

| Point | Combinational circuit | Sequential circuit |
|---|---|---|
| Output depends on | Present inputs only | Present inputs and past outputs (state) |
| Memory | None | Has memory (flip-flops) |
| Feedback | No | Yes |
| Clock | Not needed | Usually clocked |
| Speed | Faster | Slower |
| Examples | Adder, MUX, decoder, encoder | Flip-flop, register, counter |

#### JK flip-flop

The JK flip-flop is a clocked bistable circuit with inputs J, K, a clock, and outputs Q and Q'. Unlike an SR flip-flop it has no invalid state: J = K = 1 makes it toggle.

```text
 J  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[(3-in)]         ^    |
 Q' ---[      ]         |    |
 K  ---[NAND2]--R1--[NAND4]--+------ Q'
 CLK---[(3-in)]
 Q  ---[      ]
```

NAND1 (inputs J, CLK, Q') and NAND2 (inputs K, CLK, Q) are steering gates. NAND3 and NAND4 are a cross-coupled latch. The outputs Q and Q' are fed back to the input gates.

**Operation**

| J | K | Q(n+1) | Action |
|---|---|---|---|
| 0 | 0 | Q(n) | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q(n)' | Toggle |

- With CLK = 0, the steering gates output 1 and the latch holds.
- With CLK = 1, the state changes according to J and K as in the table.
- Characteristic equation: Q(n+1) = JQ' + K'Q.
- If CLK stays high longer than the gate delay with J = K = 1, the output toggles repeatedly (race-around). This is solved by edge-triggered or master-slave construction.

**Uses:** counters (J = K = 1 gives a divide-by-2 stage), registers, frequency dividers.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. A sequential circuit's output depends on:
   A. Present inputs and the past state
   B. Present inputs only
   C. Past inputs only
   D. The clock only
   Answer: A. The answer states this: Present inputs and the past state. (Key point: Output dependence)

2. Which pair gives examples of combinational circuits?
   A. Flip-flop and counter
   B. Adder and MUX
   C. Register and counter
   D. Flip-flop and register
   Answer: B. The answer states this: Adder and MUX. (Key point: Examples)

3. In the JK diagram, NAND1 and NAND2 are:
   A. The output latch
   B. Clock generators
   C. Steering gates, with NAND3 and NAND4 as the latch
   D. Reset gates
   Answer: C. The answer states this: Steering gates, with NAND3 and NAND4 as the latch. (Key point: Steering gates)

4. With J = K = 1, a JK flip-flop acts as:
   A. A memory that never changes
   B. An invalid state
   C. An AND gate
   D. A divide-by-2 stage
   Answer: D. The answer states this: A divide-by-2 stage. (Key point: Uses of JK)

## Related in Basic Electronics Engineering

- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6

## Related in other subjects

- [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6
- [Master-slave JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amaster-slave-jk) — Digital Logic, chapter 6
- [JK flip-flop with tables and timing diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-timing-diagram) — Digital Logic, chapter 6, asked 2×
- [JK flip-flop with symbol, equation, state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-state-diagram) — Digital Logic, chapter 6