---
title: "Edge triggered D flip-flop with preset, clear"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:d-flip-flop-edge-triggered"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/d-flip-flop-edge-triggered
site: BCT Engineering
---

# Edge triggered D flip-flop with preset, clear

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2067 Chaitra, 3 marks
- Video: [D Flip Flop working with PRE' and CLR' Inputs/Digital Electronics/ Flip Flops](https://www.youtube.com/watch?v=QrcRSbT0giQ) — DIGITEK KEYS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/d-flip-flop-edge-triggered
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

Draw a block diagram of edge triggered, with preset and clear facilities, D-flip flop and its truth table. State one important advantage over RS flip flop.

## Short answer

The edge-triggered D flip-flop copies D input to Q on the clock edge, with asynchrnonous preset and clear. Q(n+1)=D. It has no invalid state unlike the RS flip-flop, because internal S and R are complementary, eliminating the forbidden S=R=1 condition.

## Answer

#### Block diagram of edge-triggered D flip-flop with preset and clear

```text
          PR (preset, active low)
            |
        +---+---+
 D ---->|       |----> Q
 CLK -->|>      |
        |       |----> Q'
        +---+---+
            |
          CLR (clear, active low)
```

- **Preset (PR):** when PR = 0, Q is forced to 1 asynchronously (without the clock).
- **Clear (CLR):** when CLR = 0, Q is forced to 0 asynchronously.
- For normal clocked operation, PR = CLR = 1.

#### Truth table (positive-edge triggered)

| PR | CLR | CLK | D | Q(n+1) |
|---|---|---|---|---|
| 0 | 0 | X | X | Not allowed |
| 0 | 1 | X | X | 1 |
| 1 | 0 | X | X | 0 |
| 1 | 1 | ↑ | 0 | 0 |
| 1 | 1 | ↑ | 1 | 1 |
| 1 | 1 | 0 or 1 | X | No change |

The output copies D at the active clock edge: Q(n+1) = D.

#### Advantage over the RS flip-flop

The D flip-flop has **no invalid (forbidden) state**. It has only one data input, which is applied internally as S = D and R = D', so S and R can never both be 1. The RS flip-flop has an undefined state at S = R = 1. The D flip-flop is also simpler to use (one input), and edge triggering makes the output change only at the clock edge.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When PR = 0 (active low):
   A. Q is forced to 1 without the clock
   B. Q is forced to 0 without the clock
   C. Q copies D at the clock edge
   D. Q toggles
   Answer: A. The answer states this: Q is forced to 1 without the clock. (Key point: Preset function)

2. When CLR = 0, Q is:
   A. Forced to 1 asynchronously
   B. Forced to 0 asynchronously
   C. Equal to D
   D. Unchanged
   Answer: B. The answer states this: Forced to 0 asynchronously. (Key point: Clear function)

3. At the active clock edge, the D flip-flop:
   A. Toggles Q
   B. Sets Q to 1 always
   C. Copies D to Q, Q(n+1) = D
   D. Holds Q
   Answer: C. The answer states this: Copies D to Q, Q(n+1) = D. (Key point: D flip-flop operation)

4. The advantage of the D flip-flop over the RS is:
   A. It has no clock
   B. It needs two data inputs
   C. It is slower
   D. It has no invalid state
   Answer: D. The answer states this: It has no invalid state. (Key point: Advantage over RS)

## Related in Basic Electronics Engineering

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6

## Related in other subjects

- [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6
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- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×
- [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6