---
title: "DC load line and CE characteristics"
subject: "Basic Electronics Engineering"
chapter: 3
key: "semester_2/basic_electronics_engineering:dc-load-line-ce-characteristics"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/dc-load-line-ce-characteristics
site: BCT Engineering
---

# DC load line and CE characteristics

Basic Electronics Engineering · Chapter 3: Transistor

- Asked in: 2070 Bhadra, 2+4 marks; 2069 Poush, 1+5 marks (asked 2 times)
- Video: [DC Biasing, Load Line & Operating Point of Transistors](https://www.youtube.com/watch?v=jQb199oIY5U) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/dc-load-line-ce-characteristics
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-3

## Question

Define DC load line. Explain the common emitter configuration circuit with the help of input and output characteristics.

## Short answer

DC load line is the straight line IC = (VCC−VCE)/RC on output characteristics, showing all possible DC operating points. Saturation point (VCE≈0, IC(sat)=VCC/RC) and cut-off (IC=0, VCE=VCC). Q point is intersection with IB curve defining operating IC and VCE. CE input characteristic is IB vs VBE like forward diode; output shows saturation, active, cut-off regions, β.

## Answer

#### DC load line
The **DC load line** is the straight line on the output characteristics (IC versus VCE) that represents all possible dc operating points of a transistor for a given VCC and load resistance. It is obtained from KVL in the collector circuit: VCC = IC RC + VCE (for a circuit with the emitter grounded).

- IC = (VCC − VCE)/RC
- Point 1 (saturation, VCE ≈ 0): IC(sat) = VCC/RC
- Point 2 (cut-off, IC = 0): VCE = VCC

The **Q point** (operating point) is the intersection of the load line with the output characteristic for the chosen base current IB.

```text
 IC
 VCC/RC |\
        | \ Q
        |  *\   IB
        |    \
        +------\--- VCE
               VCC
```

#### Common emitter (CE) circuit
The input is applied between base and emitter and the output is taken between collector and emitter; the emitter is common to input and output. VBB forward biases the base-emitter junction and VCC reverse biases the base-collector junction.

```text
                         +VCC
                          |
                         [RC]
                          |
                          +------o C  (output VCE)
                        |/
 VBB (+)--[RB]--------- |   NPN
                    B   |\
                          v E
                          |
 VBB (-), GND o-----------+------o E  (common)
```

#### Input characteristics
IB versus VBE at constant VCE. It looks like a forward diode curve: negligible IB below about 0.7 V (Si), then a steep rise. A higher VCE shifts the curve slightly to the right. Input resistance ri = ΔVBE/ΔIB.

```text
 IB |        / /
    |       / /
    |      / /
    +-----/-/------ VBE
         0.7V
```

#### Output characteristics
IC versus VCE at constant IB.
```text
 IC
  |     ____ IB3
  |    /____ IB2
  |   /_____ IB1
  |  /______ IB=0
  +--------------- VCE
  sat  active
```
- **Saturation:** VCE below about 0.2 V; IC rises steeply.
- **Active:** IC ≈ β IB, nearly flat; used for amplification.
- **Cut-off:** IB = 0, IC = ICEO (small leakage).
- β = IC/IB (50 to 300); the output resistance is ro = ΔVCE/ΔIC.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. The DC load line is obtained from which relation (emitter grounded)?
   A. VCC = IB RB + VBE
   B. VCC = IC RC + VCE
   C. IC = β IB
   D. VCE = VBE + VCB
   Answer: B. KVL in the collector circuit gives VCC = IC RC + VCE, a straight line on the IC-VCE plane. (Key point: DC load line equation)

2. What are the two end points of the DC load line?
   A. IC = VCC/RC at VCE = 0, and VCE = VCC at IC = 0
   B. IC = β IB at VCE = 0, and VCE = 0.7 V at IC = 0
   C. IC = 0 at VCE = 0, and IC = VCC/RC at VCE = VCC
   D. IC = VCC/RB at VCE = 0, and VCE = VCC/RC at IC = 0
   Answer: A. Saturation point: VCE ≈ 0 so IC(sat) = VCC/RC. Cut-off point: IC = 0 so VCE = VCC. (Key point: Load line end points)

3. Where is the Q point located?
   A. At the intersection of the load line and the input characteristic
   B. At the intersection of the load line and the output characteristic for the chosen IB
   C. At the saturation end of the load line
   D. At VCE = VCC
   Answer: B. The Q point is where the load line crosses the output curve for the chosen base current. (Key point: Q point)

4. What do the CE input characteristics show?
   A. IC versus VCE at constant IB
   B. IB versus VBE at constant VCE, like a forward diode curve
   C. IC versus VCB at constant IE
   D. IB versus VCE at constant VBE
   Answer: B. Input characteristics plot IB against VBE at constant VCE; IB is negligible below about 0.7 V then rises steeply. (Key point: Input characteristics)

5. In the CE output characteristics, which region is used for amplification?
   A. Saturation, where VCE is below about 0.2 V
   B. Cut-off, where IB = 0
   C. Active, where IC ≈ β IB and is nearly flat
   D. Breakdown region
   Answer: C. In the active region IC ≈ β IB and almost independent of VCE, which gives linear amplification. (Key point: Output regions)

## Related in Basic Electronics Engineering

- [CE configuration input/output characteristics](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ace-npn-characteristics) — Basic Electronics Engineering, chapter 3, asked 3×
- [DC load line and Q-point, IB = 15 µA](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Adc-load-line-q-point-ib-15ua) — Basic Electronics Engineering, chapter 3
- [Voltage divider bias, DC load line, Q point (20 V)](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Avoltage-divider-bias-20v) — Basic Electronics Engineering, chapter 3, asked 2×
- [Voltage divider bias, DC load line, Q point (15 V)](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Avoltage-divider-bias-15v) — Basic Electronics Engineering, chapter 3, asked 2×

## Related in other subjects

- [Common emitter BJT characteristics](https://www.bctengineer.com/question.md?key=semester_1%2Ffundamental_of_electrical_and_electronics_engineering%3Ace-input-output-characteristics) — Fundamental of Electrical and Electronics Engineering, chapter 5
- [Emitter follower input/output resistance and gain](https://www.bctengineer.com/question.md?key=semester_3%2Felectronics_devices_and_circuit%3Aemitter-follower-rin-rout-gain-numeric) — Electronics Devices and Circuit, chapter 2
- [CE amplifier input, output resistance and gain (RE1, RE2)](https://www.bctengineer.com/question.md?key=semester_3%2Felectronics_devices_and_circuit%3Ace-partial-bypass-numeric) — Electronics Devices and Circuit, chapter 2
- [Emitter-bias BJT Q point and load line](https://www.bctengineer.com/question.md?key=semester_1%2Ffundamental_of_electrical_and_electronics_engineering%3Aemitter-bias-q-point) — Fundamental of Electrical and Electronics Engineering, chapter 5