---
title: "JK flip-flop operation and truth table"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:jk-flip-flop"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/jk-flip-flop
site: BCT Engineering
---

# JK flip-flop operation and truth table

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2075 Baisakh, 6 marks
- Video: [Introduction to JK flip flop](https://www.youtube.com/watch?v=j6krFp511HA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/jk-flip-flop
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

Explain the operation of JK flip-flop with necessary diagrams and characteristic table.

## Short answer

The JK flip-flop has inputs J, K, clock and outputs Q, Q'. J=0,K=0 holds state; J=0,K=1 resets to 0; J=1,K=0 sets to 1; J=1,K=1 toggles output. Characteristic equation: Q(n+1)=JQ'+K'Q. Race-around with J=K=1 is solved by edge-triggering.

## Answer

The **JK flip-flop** is a clocked flip-flop with two inputs J and K and two outputs Q and Q'. It is a refinement of the SR flip-flop in which the input J = K = 1 is allowed and makes the output toggle.

#### Block symbol

```text
        +---------+
 J ---->|         |----> Q
 CLK -->|>        |
 K ---->|         |----> Q'
        +---------+
```

#### Logic diagram (NAND gates)

```text
 J  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[(3-in)]         ^    |
 Q' ---[      ]         |    |
 K  ---[NAND2]--R1--[NAND4]--+------ Q'
 CLK---[(3-in)]
 Q  ---[      ]
```

NAND1 has inputs J, CLK and Q'. NAND2 has inputs K, CLK and Q. NAND3 and NAND4 form the cross-coupled latch. The feedback from the outputs to the input gates is the key difference from the SR flip-flop.

#### Operation

- **J = 0, K = 0:** no change, Q(n+1) = Q(n).
- **J = 0, K = 1:** reset, Q = 0.
- **J = 1, K = 0:** set, Q = 1.
- **J = 1, K = 1:** toggle, Q(n+1) = Q(n)'.

#### Characteristic table

| J | K | Q(n) | Q(n+1) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |

Characteristic equation: Q(n+1) = JQ' + K'Q.

With J = K = 1, if the clock pulse is wider than the propagation delay, the output toggles many times (race-around condition). This is removed by edge triggering or by using a master-slave JK flip-flop.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In the JK flip-flop, J = K = 1:
   A. Makes the output toggle, Q(n+1) = Q(n)'
   B. Is invalid
   C. Resets the output
   D. Holds the output
   Answer: A. The answer states this: Makes the output toggle, Q(n+1) = Q(n)'. (Key point: J = K = 1)

2. The JK characteristic equation is:
   A. Q(n+1) = JQ + K'Q'
   B. Q(n+1) = JQ' + K'Q
   C. Q(n+1) = J'Q' + KQ
   D. Q(n+1) = J + K
   Answer: B. The answer states this: Q(n+1) = JQ' + K'Q. (Key point: Characteristic equation)

3. What is the key difference from the SR logic diagram?
   A. The clock is removed
   B. There is no latch
   C. Q and Q' are fed back to the input gates
   D. It uses NOR gates
   Answer: C. The answer states this: Q and Q' are fed back to the input gates. (Key point: Feedback)

4. Race-around is removed by:
   A. Using a longer clock pulse
   B. Setting J = K = 0
   C. Removing the clock
   D. Edge triggering or a master-slave arrangement
   Answer: D. The answer states this: Edge triggering or a master-slave arrangement. (Key point: Race-around)

## Related in Basic Electronics Engineering

- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6

## Related in other subjects

- [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2×
- [Edge triggered JK flip-flop with excitation table](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-excitation) — Digital Logic, chapter 6
- [JK over SR advantages; D flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-over-sr-d-flipflop) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×