--- title: "K-map with don't cares, NAND only" subject: "Basic Electronics Engineering" chapter: 6 key: "semester_2/basic_electronics_engineering:kmap-dont-care-nand" source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/kmap-dont-care-nand site: BCT Engineering --- # K-map with don't cares, NAND only Basic Electronics Engineering · Chapter 6: Digital Electronics - Asked in: 2070 Magh, 3+3 marks - Video: [Don't Care Conditions in Karnaugh Map (with Solved Examples)](https://www.youtube.com/watch?v=ZayoUTi2tsA) — ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/kmap-dont-care-nand - Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6 ## Question Simplify the given function using K-map method. F(A,B,C) = Σ(0, 1, 2, 5) + D(3, 4, 6) and implement the simplified circuit using NAND only. ## Short answer With don't-cares d(3,4,6), K-map groups: row A=0 gives A', columns B=0 gives B'. Simplified F = A' + B'. Using De Morgan, F = (AB)' realized by a single NAND gate. ## Answer F(A,B,C) = Σm(0, 1, 2, 5) + d(3, 4, 6). #### K-map (X = don't care) ```text BC 00 01 11 10 A = 0 | 1 | 1 | X | 1 | A = 1 | X | 1 | 0 | X | ``` #### Grouping - Quad (m0, m1, m3, m2): the whole row A = 0, using the don't care m3, gives **A'**. - Quad (m0, m1, m4, m5): B = 0 (columns 00 and 01), using the don't care m4, gives **B'**. All the 1s (0, 1, 2, 5) are covered. **Simplified: F = A' + B'** #### NAND-only implementation By De Morgan's theorem: A' + B' = (A·B)'. That is a single 2-input NAND gate. ```text A ---+ [NAND]---- F = (AB)' = A' + B' B ---+ ``` Check: F = 0 only for A = B = 1 (m7), which is the only required 0. So one NAND gate is enough. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Don't-care cells in a K-map are used to: A. Make groups larger when this helps simplification B. Be always treated as 0 C. Be always treated as 1 D. Be removed from the map Answer: A. The answer states this: Make groups larger when this helps simplification. (Key point: Role of don't care) 2. The row A = 0 forms a quad giving A' by using don't care: A. m4 B. m3 C. m6 D. m7 Answer: B. The answer states this: m3. (Key point: Group A') 3. The quad (m0, m1, m4, m5) gives: A. A' B. C' C. B' D. A'B' Answer: C. The answer states this: B'. (Key point: Group B') 4. F = A' + B' is realized by: A. Two NAND gates and a NOT B. A single NOR gate C. An AND gate followed by an OR gate D. A single 2-input NAND gate Answer: D. The answer states this: A single 2-input NAND gate. (Key point: NAND implementation) ## Related in Basic Electronics Engineering - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6 - [K-map: A'B + BC' + AC'](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-abc-simple) — Basic Electronics Engineering, chapter 6, asked 2× - [K-map: x'yz + x'y'z + xyz with gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-realize-gates) — Basic Electronics Engineering, chapter 6, asked 2× - [K-map: 4-variable minterm list](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-4var-sigma) — Basic Electronics Engineering, chapter 6 - [K-map: 3-variable five-term expression](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-xyz-five-term) — Basic Electronics Engineering, chapter 6 - [K-map: A'BC' + ABC' + ABC](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-abc-three-term) — Basic Electronics Engineering, chapter 6 ## Related in other subjects - [K-map Σ(0,1,4,8,10,11,12)+d, NAND-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nand-only-01248) — Digital Logic, chapter 3 - [K-map Σm(7,9,12,13,14,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-sum-7-9-12) — Digital Logic, chapter 3 - [K-map Σm(0,1,2,4,7,8,9,10,12,15)+d, NOR-only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-nor-only-01247) — Digital Logic, chapter 3 - [Minterms/maxterms; K-map Σm(0,1,2,4,5,9,12,15)+d, NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aminterm-maxterm-kmap-nand-0124) — Digital Logic, chapter 3