--- title: "N-channel enhancement MOSFET construction, working" subject: "Basic Electronics Engineering" chapter: 3 key: "semester_2/basic_electronics_engineering:mosfet-n-channel-enhancement" source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/mosfet-n-channel-enhancement site: BCT Engineering --- # N-channel enhancement MOSFET construction, working Basic Electronics Engineering · Chapter 3: Transistor - Asked in: 2074 Bhadra, 6 marks; 2072 Magh, 6 marks; 2071 Magh, 6 marks; 2068 Bhadra, 7 marks; 2067 Mangsir, 7 marks; 2067 Chaitra, 4 marks (asked 6 times) - Video: [MOSFET - Enhancement Type MOSFET Explained (Construction, Working and Characteristics Explained)](https://www.youtube.com/watch?v=l9LBIy9Ioxo) — ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/mosfet-n-channel-enhancement - Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-3 ## Question Describe the construction and working principle of n-channel enhancement type MOSFET with necessary diagrams. ## Short answer An n-channel enhancement MOSFET is built on a p‑substrate with n⁺ source/drain regions, a SiO₂ insulator, and a gate electrode. There is no initial channel. Positive gate voltage above threshold VT attracts electrons, forming an n‑type inversion channel. Drain current ID = k(VGS−VT)² in saturation. Very high input resistance. ## Answer A **MOSFET** (metal oxide semiconductor field effect transistor) is a voltage-controlled device in which the gate is insulated from the channel by a thin silicon dioxide layer. The **n-channel enhancement MOSFET (E-MOSFET)** has no channel at zero gate voltage; the channel is created (enhanced) by applying a positive gate voltage. #### Construction - A lightly doped p-type substrate (body). - Two heavily doped n⁺ regions diffused into the substrate: the **source (S)** and **drain (D)**. - A thin layer of SiO₂ (insulator) over the region between source and drain. - A metal (or polysilicon) **gate (G)** over the oxide. There is no physical channel between S and D. - The substrate is usually connected to the source. ```text S G D | +-----+ | ---+ |metal| +--- | n+| +-----+ | n+ | | |==== SiO2 ==== | | p-type substrate | +----------B-----------+ ``` #### Working principle 1. **VGS = 0:** between the n⁺ source and drain there are two back-to-back PN junctions, so no current flows. ID ≈ 0. 2. **Small positive VGS:** the gate attracts electrons and repels holes from the substrate surface under the oxide, forming a depletion region. 3. **VGS ≥ VT (threshold voltage):** enough electrons collect under the oxide to form a thin **n-type inversion layer (channel)** between source and drain. Increasing VGS further enhances the channel and increases the current. 4. **With VDS applied:** electrons flow from the source through the channel to the drain; the conventional current ID flows from drain to source. #### Operating regions - **Cut-off:** VGS < VT, ID = 0. - **Ohmic (triode) region:** VDS < VGS − VT; the channel acts as a resistor; ID = k[2(VGS − VT)VDS − VDS²]. - **Saturation:** VDS ≥ VGS − VT; the channel pinches off near the drain and ID = k(VGS − VT)², nearly independent of VDS. ```text ID ID | VGS3 ___ | / | VGS2 ___ | / | VGS1 ___ | / | VT