---
title: "Multiplexer and 4:1 MUX"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:multiplexer-4-1"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/multiplexer-4-1
site: BCT Engineering
---

# Multiplexer and 4:1 MUX

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2075 Baisakh, 6 marks; 2068 Magh, 3 marks (asked 2 times)
- Video: [Introduction to Multiplexers | MUX Basic](https://www.youtube.com/watch?v=FKvnmxte98A) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/multiplexer-4-1
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

What is multiplexer (MUX)? Explain 4:1 Multiplexer.

## Short answer

A multiplexer (MUX) is a combinational circuit that selects one of many inputs to a single output under select lines. A 4:1 MUX has four data inputs (I0-I3), two selects (S1,S0), and output Y = S1'S0'I0 + S1'S0 I1 + S1 S0' I2 + S1 S0 I3. Implemented with inverters, AND gates and an OR gate.

## Answer

A **multiplexer (MUX)** is a combinational circuit that selects one of many input lines and sends it to a single output line, under the control of select lines. It is also called a "data selector". A 2ⁿ:1 MUX has 2ⁿ data inputs, n select lines and one output.

#### 4:1 multiplexer

It has four data inputs (I0 to I3), two select lines (S1, S0) and one output Y.

```text
         +-----------+
 I0 -----|0          |
 I1 -----|1   4:1    |
 I2 -----|2   MUX    |---- Y
 I3 -----|3          |
         +--+----+---+
            |    |
           S1   S0
```

**Function table**

| S1 | S0 | Y |
|---|---|---|
| 0 | 0 | I0 |
| 0 | 1 | I1 |
| 1 | 0 | I2 |
| 1 | 1 | I3 |

**Boolean expression:**

Y = S1'S0' I0 + S1'S0 I1 + S1 S0' I2 + S1 S0 I3

**Gate implementation:** two NOT gates for S1' and S0'; four 3-input AND gates, each combining one input with its matching select combination; and one 4-input OR gate to give Y.

```text
 I0 -[AND: S1' S0']--+
 I1 -[AND: S1' S0 ]--+--[OR]-- Y
 I2 -[AND: S1  S0']--+
 I3 -[AND: S1  S0 ]--+
```

Applications: data routing, parallel-to-serial conversion, implementing Boolean functions, and communication systems (time-division multiplexing).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. A multiplexer is:
   A. A combinational circuit that selects one of many inputs and sends it to one output
   B. A circuit that sends one input to many outputs
   C. A sequential circuit with memory
   D. A circuit that stores bits
   Answer: A. The answer states this: A combinational circuit that selects one of many inputs and sends it to one output. (Key point: Multiplexer definition)

2. A 4:1 MUX has:
   A. 2 data inputs, 4 select lines, 1 output
   B. 4 data inputs, 2 select lines, 1 output
   C. 4 data inputs, 4 select lines, 1 output
   D. 4 data inputs, 1 select line, 2 outputs
   Answer: B. The answer states this: 4 data inputs, 2 select lines, 1 output. (Key point: Number of select lines)

3. For S1 S0 = 10, the output Y equals:
   A. I1
   B. I3
   C. I2
   D. I0
   Answer: C. The answer states this: I2. (Key point: Select code)

4. A 4:1 MUX using gates needs:
   A. Four NOT and two OR
   B. One AND and four OR
   C. Two flip-flops and four AND
   D. Two NOT, four 3-input AND and one 4-input OR
   Answer: D. The answer states this: Two NOT, four 3-input AND and one 4-input OR. (Key point: Gate implementation)

## Related in other subjects

- [Multiplexer tree; 16:1 MUX from 4:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-16to1-from-4to1) — Digital Logic, chapter 4
- [8:1 MUX operation; 32:1 MUX from 8:1](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-32to1-tree) — Digital Logic, chapter 4
- [32:1 MUX tree; implement Σm(0,1,3,8,9,13,15)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-32to1-tree-function-15) — Digital Logic, chapter 4
- [K-map ΠM(0,2,4,6,7,8,10,13,15) and 8:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-pom-8to1-mux) — Digital Logic, chapter 3