---
title: "SR flip-flop operation"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:sr-flip-flop"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/sr-flip-flop
site: BCT Engineering
---

# SR flip-flop operation

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2074 Bhadra, 6 marks; 2073 Magh, 5 marks; 2071 Bhadra, 6 marks; 2071 Magh, 4 marks; 2070 Bhadra, 5 marks; 2068 Bhadra, 6 marks (asked 6 times)
- Video: [Introduction to SR Flip Flop](https://www.youtube.com/watch?v=HZg7fNu-l24) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/sr-flip-flop
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

Explain the operation of SR (clocked R-S) flip-flop with necessary circuit/diagram and characteristic table.

## Short answer

The clocked SR flip-flop is a bistable element storing one bit. When clock is high, S=1,R=0 sets Q=1; S=0,R=1 resets Q=0; S=R=0 holds state; S=R=1 is forbidden. It uses steering gates and a cross-coupled NAND latch. Characteristic table: (0,0)→Q(n); (0,1)→0; (1,0)→1; (1,1)→?

## Answer

A **flip-flop** is a bistable circuit with two stable states that can store one bit of data. The **clocked SR flip-flop** is the basic flip-flop where S (set) and R (reset) inputs act only when the clock pulse (CLK) is high.

#### Circuit (NAND gates)

```text
 S  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[      ]       ^  \   |
                      |   \  |
                      |    \ v
 CLK---[NAND2]--R1--[NAND4]--+------ Q'
 R  ---[      ]
```

Gates 1 and 2 are steering gates: S1 = (S·CLK)' and R1 = (R·CLK)'. Gates 3 and 4 are a cross-coupled NAND latch: Q = (S1·Q')' and Q' = (R1·Q)' (Q' feeds gate 3 and Q feeds gate 4).

Block symbol:

```text
      +-------+
  S --|       |-- Q
 CLK -|>      |
  R --|       |-- Q'
      +-------+
```

#### Operation

- **CLK = 0:** the steering gates give 1, so the latch holds its previous state.
- **CLK = 1 and S = 0, R = 0:** no change, Q(n+1) = Q(n).
- **S = 0, R = 1:** reset, Q = 0.
- **S = 1, R = 0:** set, Q = 1.
- **S = 1, R = 1:** both outputs are forced to the same level, and when the clock returns to 0 the final state is unpredictable. So this condition is **invalid (forbidden)**.

#### Characteristic table

| S | R | Q(n+1) | Meaning |
|---|---|---|---|
| 0 | 0 | Q(n) | No change |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ? | Invalid |

Characteristic equation: Q(n+1) = S + R'Q(n), with the condition S·R = 0.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When CLK = 0 in the clocked SR flip-flop:
   A. The steering gates give 1 and the latch holds its previous state
   B. The output is set to 1
   C. The output is reset to 0
   D. The output becomes invalid
   Answer: A. The answer states this: The steering gates give 1 and the latch holds its previous state. (Key point: Clock low behaviour)

2. Why is S = R = 1 forbidden?
   A. It resets the flip-flop
   B. Both outputs are forced to the same level, and the final state is unpredictable
   C. It toggles the output
   D. It sets the flip-flop permanently
   Answer: B. The answer states this: Both outputs are forced to the same level, and the final state is unpredictable. (Key point: Invalid condition)

3. With CLK = 1, S = 1 and R = 0, the flip-flop:
   A. Resets, Q = 0
   B. Holds its state
   C. Sets, Q = 1
   D. Toggles
   Answer: C. The answer states this: Sets, Q = 1. (Key point: Set and reset)

4. The characteristic equation of the SR flip-flop is:
   A. Q(n+1) = S'R + Q(n)
   B. Q(n+1) = SR + Q'(n)
   C. Q(n+1) = S.R'Q(n)'
   D. Q(n+1) = S + R'Q(n) with S.R = 0
   Answer: D. The answer states this: Q(n+1) = S + R'Q(n) with S.R = 0. (Key point: Characteristic equation)

## Related in Basic Electronics Engineering

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Wien bridge oscillator circuit and operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Awien-bridge-draw-explain) — Basic Electronics Engineering, chapter 4, asked 4×

## Related in other subjects

- [SR flip-flop diagram, excitation table, equation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-flipflop-diagram-equation) — Digital Logic, chapter 6
- [SR drawbacks; D flip-flop operation](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-d-flipflop) — Digital Logic, chapter 6
- [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×