---
title: "X-OR gate using NAND gates only"
subject: "Basic Electronics Engineering"
chapter: 6
key: "semester_2/basic_electronics_engineering:xor-using-nand"
source: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/xor-using-nand
site: BCT Engineering
---

# X-OR gate using NAND gates only

Basic Electronics Engineering · Chapter 6: Digital Electronics

- Asked in: 2070 Bhadra, 2 marks
- Video: [Implement EX-OR gate  using NAND gate](https://www.youtube.com/watch?v=owpm6DM67U8) — SGR CompTech
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_2/basic_electronics_engineering/xor-using-nand
- Whole chapter: https://www.bctengineer.com/md/semester_2/basic_electronics_engineering/chapter-6

## Question

Draw the circuit of X-OR gate using NAND gates only.

## Short answer

Use four 2-input NAND gates. N1 = NAND(A,B); N2 = NAND(A, N1); N3 = NAND(B, N1); N4 = NAND(N2,N3) yields A XOR B.

## Answer

The XOR function is Y = A⊕B = A'B + AB' and is built from four 2-input NAND gates.

```text
 A ---+------------------[N2]---+
      |        +--------/       |
      +--[N1]--+                [N4]--- Y
      |        +--------\       |
 B ---+------------------[N3]---+
```

(N1 takes A and B; its output goes to both N2 and N3. N2 also takes A, and N3 also takes B.)

- N1 = NAND(A, B) = (AB)'
- N2 = NAND(A, N1) = (A·(AB)')' = (A·(A' + B'))' = (AB')'
- N3 = NAND(B, N1) = (B·(AB)')' = (A'B)'
- N4 = NAND(N2, N3) = ((AB')' · (A'B)')' = AB' + A'B = A⊕B

Check by truth table: for A = 1, B = 0: N1 = 1, N2 = (1·1)' = 0, N3 = (0·1)' = 1, Y = (0·1)' = 1. For A = B = 1: N1 = 0, N2 = N3 = 1, Y = (1·1)' = 0.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. An XOR gate built with NAND gates uses:
   A. Four 2-input NAND gates
   B. Two 2-input NAND gates
   C. Three 2-input NAND gates
   D. Five 2-input NAND gates
   Answer: A. The answer states this: Four 2-input NAND gates. (Key point: Number of NAND gates)

2. N1 in the XOR circuit gives:
   A. A'B
   B. (AB)'
   C. AB
   D. A+B
   Answer: B. The answer states this: (AB)'. (Key point: N1 output)

3. N2 = NAND(A, N1) equals:
   A. (A'B)'
   B. AB'
   C. (AB')'
   D. A + B
   Answer: C. The answer states this: (AB')'. (Key point: N2 output)

4. N4 = NAND(N2, N3) gives:
   A. AB + A'B'
   B. A + B
   C. (AB)'
   D. AB' + A'B
   Answer: D. The answer states this: AB' + A'B. (Key point: Final output)

## Related in Basic Electronics Engineering

- [K-map with don't cares, NAND only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Akmap-dont-care-nand) — Basic Electronics Engineering, chapter 6
- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [Encoder; NAND and XOR truth tables](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aencoder-truth-tables) — Basic Electronics Engineering, chapter 6

## Related in other subjects

- [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2×
- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×
- [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2
- [Universal gates; Ex-OR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-xor-nand) — Digital Logic, chapter 2