---
title: "Circuit to add 1011 and 1100"
subject: "Digital Logic"
chapter: 5
key: "semester_3/digital_logic:add-1011-1100-circuit"
source: https://www.bctengineer.com/q/semester_3/digital_logic/add-1011-1100-circuit
site: BCT Engineering
---

# Circuit to add 1011 and 1100

Digital Logic · Chapter 5: Arithmetic Circuits

- Asked in: 2081 Baisakh, 5 marks; 2074 Chaitra, 3 marks (asked 2 times)
- Video: [4 Bit Parallel Adder using Full Adders](https://www.youtube.com/watch?v=NO7Gt8IDSGA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/add-1011-1100-circuit
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5

## Question

Design and explain the circuit to add the following bits 1011 and 1100 using block-diagrams.

## Short answer

A 4-bit parallel adder adds 1011 and 1100. LSB: 1+0=1, carry 0; next: 1+0=1, carry 0; next: 0+1=1, carry 0; MSB: 1+1=0, carry 1. Final sum is 10111 (23 in decimal).

## Answer

Two 4-bit numbers are added with a **4-bit parallel (ripple-carry) adder**: four full adders, one for each bit position, with the carry of each stage feeding the next. The first stage's carry-in is 0 (a half adder could be used there).

Let $A = A_3A_2A_1A_0 = 1011$ and $B = B_3B_2B_1B_0 = 1100$.

#### Block diagram

```text
   A3 B3     A2 B2     A1 B1     A0 B0
   1  1      0  1      1  0      1  0
   |  |      |  |      |  |      |  |
  +-----+   +-----+   +-----+   +-----+
C4<| FA3 |<C3| FA2 |<C2| FA1 |<C1| FA0 |<-C0=0
  +-----+   +-----+   +-----+   +-----+
     |         |         |         |
     S3        S2        S1        S0
```

Each full adder computes
$$
S_i = A_i \oplus B_i \oplus C_i, \qquad C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)
$$

#### Working, stage by stage

| Stage | $A_i$ | $B_i$ | $C_i$ | $S_i$ | $C_{i+1}$ |
|---|---|---|---|---|---|
| FA0 | 1 | 0 | 0 | 1 | 0 |
| FA1 | 1 | 0 | 0 | 1 | 0 |
| FA2 | 0 | 1 | 0 | 1 | 0 |
| FA3 | 1 | 1 | 0 | 0 | 1 |

1. FA0 adds the LSBs 1 + 0 with $C_0 = 0$: sum 1, carry 0.
2. FA1 adds 1 + 0 + 0: sum 1, carry 0.
3. FA2 adds 0 + 1 + 0: sum 1, carry 0.
4. FA3 adds 1 + 1 + 0: sum 0, carry 1, which appears as $C_4$ (the fifth bit of the result).

**Answer:** $1011 + 1100 = 10111_2$ ($C_4 = 1$, $S_3S_2S_1S_0 = 0111$). Check: $11 + 12 = 23 = 10111_2$.

All bits are applied at the same time (parallel), but the final result is valid only after the carry has rippled through all four stages. IC 7483/74283 is a ready-made 4-bit parallel adder.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What circuit adds two 4-bit numbers here?
   A. Four full adders in cascade (ripple-carry)
   B. A single half adder
   C. Four half adders in parallel with no carry
   D. A 4:1 MUX
   Answer: A. Each stage's carry out feeds the next stage's carry in. (Key point: Adder structure)

2. What is C0 for the first stage in plain addition?
   A. 1
   B. 0
   C. A3
   D. B0
   Answer: B. No carry enters the LSB for plain addition. (Key point: Initial carry)

3. What is 1011 + 1100?
   A. 01111
   B. 11000
   C. 10111 (C4 = 1, sum 0111)
   D. 10101
   Answer: C. 11 + 12 = 23 = 10111. (Key point: Result)

4. When is the sum output valid?
   A. Immediately when inputs are applied
   B. Only after the clock edge
   C. After C0 is set to 1
   D. After the carry has rippled through all stages
   Answer: D. Higher stages must wait for the carry from lower stages. (Key point: Output validity)

## Related in Digital Logic

- [PISO shift register with 1011 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1011-store-retrieve) — Digital Logic, chapter 7, asked 4×
- [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4
- [Parity bits and 3-bit even parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-even-generator-3bit) — Digital Logic, chapter 4, asked 2×
- [Parity bits and 3-bit odd parity generator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparity-odd-generator-3bit) — Digital Logic, chapter 4, asked 2×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×

## Related in other subjects

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