--- title: "Comb vs seq; asynchronous decade counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-decade-comb-seq" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-decade-comb-seq site: BCT Engineering --- # Comb vs seq; asynchronous decade counter Digital Logic · Chapter 8: Counters - Asked in: 2080 Bhadra, 1+6 marks - Video: [Comparison between Combinational and Sequential Circuits](https://www.youtube.com/watch?v=SzV4l0_1MCQ) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-decade-comb-seq - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Differentiate between combinational and sequential circuits. Explain the operation of asynchronous decade counter with timing diagrams. ## Short answer Combinational circuits depend only on present inputs; sequential circuits store state. An asynchronous decade counter uses four cascaded JK flip-flops (J=K=1) clocked by the previous Q output. A NAND of Q3 and Q1 clears all flip-flops when count reaches 1010, recycling to 0000 after count 9. ## Answer #### Combinational vs sequential circuits | Point | Combinational circuit | Sequential circuit | |---|---|---| | Output depends on | Present inputs only | Present inputs and past state | | Memory | No memory | Has memory (flip-flops/latches) | | Feedback | No feedback path | Feedback from output to input | | Clock | Not needed | Usually clocked | | Analysis tool | Truth table | State table / state diagram | | Examples | Adder, MUX, decoder | Flip-flop, register, counter | #### Asynchronous decade counter It counts 0000 to 1001 (0–9) and resets on the 10th pulse. **Circuit:** four negative-edge JK flip-flops with $J = K = 1$. CLK → FF0; $Q_0$, $Q_1$, $Q_2$ clock FF1, FF2, FF3. A NAND of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q1 ---| | ``` **Operation** 1. Start at 0000. FF0 toggles on every falling clock edge. 2. FF1 toggles when $Q_0$ goes 1→0, FF2 when $Q_1$ goes 1→0, FF3 when $Q_2$ goes 1→0, so the count rises by one per pulse: 0, 1, …, 9. 3. On the 10th pulse the outputs try to become 1010. Since $Q_3 = Q_1 = 1$, the NAND output goes low and clears all flip-flops to 0000. The 1010 state lasts only a few nanoseconds. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 0 ``` $Q_3$ is high for counts 8 and 9 and gives $f_{clk}/10$. Example IC: 7490. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the main difference between combinational and sequential circuits? A. Combinational circuits always use a clock B. Sequential outputs depend on present inputs and past state; combinational depend on present inputs only C. Combinational circuits use flip-flops for memory D. Sequential circuits have no feedback Answer: B. Sequential circuits have memory and feedback, so past state affects the output; combinational circuits do not. (Key point: Combinational vs sequential) 2. Which gate clears the asynchronous decade counter on the 10th pulse? A. NAND of Q3 and Q1 B. NAND of Q3 and Q0 C. AND of Q2 and Q1 D. NOR of Q3 and Q2 Answer: A. 1010 is the first state with Q3 = Q1 = 1, so NAND(Q3,Q1) goes low and clears all flip-flops. (Key point: Reset gate of decade counter) 3. In the negative-edge asynchronous decade counter, when does FF1 toggle? A. On every clock edge B. When Q0 goes from 1 to 0 C. When Q3 goes high D. When the NAND output goes high Answer: B. Each stage is clocked by the previous Q, and a negative-edge FF toggles when that Q falls 1 to 0. (Key point: Ripple clocking) 4. What is true about state 1010 in this counter? A. It is a stable counted state B. It lasts only a few nanoseconds before being cleared C. It is never reached D. It lasts one full clock period Answer: B. The outputs briefly reach 1010, the NAND clears them almost immediately, so it is only a short glitch state. (Key point: Transient state) ## Close variants set in other exams - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Comb vs seq; synchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-decade-comb-seq) — Digital Logic, chapter 8, asked 2× ## Related in Digital Logic - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [Asynchronous (ripple) decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aripple-decade-counter) — Digital Logic, chapter 8, asked 2× - [Synchronous decade counter with timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asynchronous-decade-counter) — Digital Logic, chapter 8, asked 2× - [Combinational vs sequential; BCD-to-decimal decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-to-decimal-decoder) — Digital Logic, chapter 4 - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Synchronous vs asynchronous circuits; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-async-sr-to-jk) — Digital Logic, chapter 6 ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6