--- title: "Synchronous circuits; asynchronous decade counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-decade-counter-define" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-decade-counter-define site: BCT Engineering --- # Synchronous circuits; asynchronous decade counter Digital Logic · Chapter 8: Counters - Asked in: 2078 Bhadra, 1+6 marks - Video: [mod 10 asynchronous counter](https://www.youtube.com/watch?v=k7dL2Sbr7Z4) — Justin John - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-decade-counter-define - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define synchronous sequential circuits. Explain the operation of asynchronous decade counter with timing diagrams and circuit diagram. ## Short answer Synchronous sequential circuits change state on a common clock edge. Asynchronous decade (mod-10) counter uses 4 JK flip-flops with J=K=1; a NAND of Q3 and Q1 clears counter at 1010, counting 0-9 then reset. Output Q3 divides clock by 10. ## Answer #### Synchronous sequential circuit A **synchronous sequential circuit** is a sequential circuit whose state changes only at discrete instants fixed by a common clock signal (at the clock edge). All memory elements (flip-flops) are driven by the same clock, so the outputs are predictable and free of timing races. #### Asynchronous decade counter An asynchronous decade (mod-10) counter counts 0 (0000) to 9 (1001) and resets on the 10th clock pulse. **Circuit:** four negative-edge triggered JK flip-flops with $J = K = 1$. CLK drives FF0; $Q_0$, $Q_1$, $Q_2$ drive the clocks of FF1, FF2, FF3. A NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q1 ---| | ``` **Operation** 1. All flip-flops are cleared first, so the count is 0000. 2. FF0 toggles on each falling edge of CLK. FF1 toggles whenever $Q_0$ goes 1→0, FF2 whenever $Q_1$ goes 1→0, FF3 whenever $Q_2$ goes 1→0. This produces the binary up count. 3. On the 10th pulse the outputs reach 1010. This is the first state with $Q_3 = Q_1 = 1$, so the NAND output goes low and clears all flip-flops to 0000. The counter therefore has 10 stable states (0–9). | Clock | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | |---|---|---|---|---|---|---|---|---|---|---|---| | Q3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | | Q2 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | Q1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | | Q0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 0 ``` Each stage changes on the falling edge of the stage before it. $Q_3$ gives one pulse for every 10 clock pulses ($f_{clk}/10$). Because the stages change one after another, the real outputs are delayed by $t_{pd}$ per stage and a short glitch appears at the reset (state 1010). IC 7490 is a commercial decade ripple counter. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What defines a synchronous sequential circuit? A. Its state changes whenever any input changes B. Its state changes only at instants fixed by a common clock C. It has no memory elements D. Its outputs depend on present inputs only Answer: B. All memory elements share a common clock, so state changes only at the clock edge. (Key point: Synchronous sequential circuit) 2. Which state is decoded to reset the asynchronous decade counter, and why? A. 1001, because it is the last valid count B. 1010, because Q3 and Q1 are both 1 for the first time C. 1111, because all outputs are 1 D. 1100, because Q3 and Q2 are both 1 Answer: B. Counts 0-9 never have Q3 = Q1 = 1, so 1010 is the first such state; the NAND of Q3 and Q1 clears all flip-flops. (Key point: Reset state of decade counter) 3. How are the stages clocked in the ripple decade counter? A. CLK drives all four flip-flops B. CLK drives FF0 and each later FF is clocked by the previous Q output C. CLK drives FF3 and the rest follow from Q3 D. Each FF is clocked by the NAND output Answer: B. Only FF0 receives CLK; Q0, Q1, Q2 clock FF1, FF2, FF3 respectively, so the stages change one after another. (Key point: Clock connection) 4. What is the effect of the reset at state 1010 and the output frequency of Q3? A. No glitch; Q3 gives f/10 B. A short glitch appears at 1010; Q3 gives f/10 C. A short glitch appears; Q3 gives f/16 D. No glitch; Q3 gives f/5 Answer: B. Because the stages ripple, 1010 exists briefly before clearing, causing a glitch. Counting 10 states makes Q3 = f_clk/10. (Key point: Glitch and frequency) ## Close variants set in other exams - [Comb vs seq; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-comb-seq) — Digital Logic, chapter 8, asked 4× ## Related in Digital Logic - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [Synchronous decade counter with timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asynchronous-decade-counter) — Digital Logic, chapter 8, asked 2× - [Comb vs seq; synchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-decade-comb-seq) — Digital Logic, chapter 8, asked 2× - [Asynchronous (ripple) decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aripple-decade-counter) — Digital Logic, chapter 8, asked 2× - [Synchronous vs asynchronous circuits; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-async-sr-to-jk) — Digital Logic, chapter 6 - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× ## Related in other subjects - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Multiplexing; synchronous vs asynchronous TDM](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Amux-compare-sync-async-tdm) — Data Communication, chapter 6, asked 6× - [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3×