--- title: "4-bit asynchronous down counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-down-counter-4bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-down-counter-4bit site: BCT Engineering --- # 4-bit asynchronous down counter Digital Logic · Chapter 8: Counters - Asked in: 2075 Chaitra, 6 marks - Video: [3 bit & 4 bit Asynchronous Down Counter](https://www.youtube.com/watch?v=noUcCs2zNaI) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-down-counter-4bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Explain the working principle of 4 bit down asynchronous counter with neat timing diagram using negative clock edge triggering. ## Short answer A 4-bit asynchronous down counter uses four negative-edge JK flip-flops (J=K=1), each clocked by Q' of the preceding stage. Starting from 0000, the first pulse toggles all to 1111, then it counts down 15,14,…,0. Q0 divides clock by 2, Q1 by 4, Q2 by 8, and Q3 by 16. ## Answer A **4-bit asynchronous down counter** counts 15, 14, 13, …, 0 and then back to 15, decreasing by one on every clock pulse. Only the first flip-flop gets the external clock. #### Principle In a down count a flip-flop must toggle when the next lower bit changes from **0 to 1** (a "borrow"). With negative-edge triggered flip-flops, a 0→1 change of $Q$ is a 1→0 change of $\overline{Q}$. So each stage is clocked from the $\overline{Q}$ of the previous stage. #### Circuit Four negative-edge JK flip-flops, all with $J = K = 1$ (toggle mode). CLK → FF0; $\overline{Q_0}$ → FF1; $\overline{Q_1}$ → FF2; $\overline{Q_2}$ → FF3. The count is read from $Q_3Q_2Q_1Q_0$. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3 +-----+ +-----+ +-----+ +-----+ ``` #### Working 1. Start with 0000. On the first falling edge FF0 toggles: $Q_0$ goes 0→1, so $\overline{Q_0}$ falls and FF1 toggles; $Q_1$ goes 0→1, so FF2 toggles; and then FF3 toggles. The count becomes **1111** (15). 2. Next edge: $Q_0$ goes 1→0, $\overline{Q_0}$ rises, so FF1 does not change: **1110** (14). 3. Next edge: $Q_0$ 0→1 toggles FF1 ($Q_1$ 1→0), which does not clock FF2: **1101** (13). 4. The count keeps falling by one per pulse: 12, 11, …, 1, 0, and then 15 again. | Clock | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |---|---|---|---|---|---|---|---|---|---| | Q3Q2Q1Q0 | 0000 | 1111 | 1110 | 1101 | 1100 | 1011 | 1010 | 1001 | 1000 | | Count | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | and continuing 0111 (7), 0110 (6), …, 0000 (0). #### Timing diagram (falling-edge clock) ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________ Q2 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾ Q1 ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 15 14 13 12 11 10 9 8 7 6 5 4 ``` Each $Q$ changes when the $Q$ of the stage before it goes **high** (its $\overline{Q}$ falls). In practice each stage adds a delay $t_{pd}$, so the change from 0000 to 1111 takes $4\,t_{pd}$. The circuit also divides frequency: $Q_0 = f/2$, $Q_1 = f/4$, $Q_2 = f/8$, $Q_3 = f/16$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In a down counter, when must a stage toggle? A. When the lower bit changes from 1 to 0 B. When the lower bit changes from 0 to 1 (a borrow) C. On every clock edge D. When the lower bit is steady at 1 Answer: B. Counting down, a higher bit changes when the lower bit borrows, i.e. goes 0 to 1. (Key point: When a down-counter stage toggles) 2. With negative-edge triggered flip-flops, how is each stage clocked? A. From Q of the previous stage B. From Q' of the previous stage C. From the external clock D. From Q of the next stage Answer: B. A 0 to 1 change of Q is a 1 to 0 change of Q', which a negative-edge flip-flop senses. (Key point: Clock connection) 3. From 0000, what is the count after the first falling edge and why? A. 0001, because FF0 toggles only B. 1111, because the borrow ripples through all stages C. 1110, because FF0 holds D. 0000, nothing changes Answer: B. Q0 goes 0 to 1, so Q0' falls and FF1 toggles, and so on up to FF3, giving 1111 (15). (Key point: First count) 4. How long does the 0000 to 1111 change take and what does Q3 output? A. 1 t_pd; f/2 B. 4 t_pd; f/16 C. 4 t_pd; f/8 D. 2 t_pd; f/16 Answer: B. Four stages ripple one after another, giving 4 t_pd, and Q3 divides the clock by 16. (Key point: Delay and division) ## Related in Digital Logic - [3-bit asynchronous up/down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-up-down-counter-3bit) — Digital Logic, chapter 8, asked 2× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8 - [Ripple counter; asynchronous mod-11 up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod11-up-counter) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8 ## Related in other subjects - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Working principle of dc generator with diagram](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machines%3Adc-generator-principle-diagram) — Electrical Machines, chapter 3 - [Digital clock state diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Adigital-clock-state-diagram) — Object Oriented Analysis and Design, chapter 2