--- title: "Ripple counter; asynchronous mod-11 up counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod11-up-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod11-up-counter site: BCT Engineering --- # Ripple counter; asynchronous mod-11 up counter Digital Logic · Chapter 8: Counters - Asked in: 2080 Bhadra, 2+6 marks - Video: [Design MOD 11 Asynchronous Up Counter Using JK Flip Flop | MOD 11 Ripple Counter | Counter](https://www.youtube.com/watch?v=oPyK1NlBFC4) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod11-up-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define a ripple counter. Design an asynchronous mod-11 up-counter with negative edge triggering clock. ## Short answer A ripple counter is an asynchronous counter where only the first flip-flop receives the external clock; later stages are clocked by previous Q outputs, causing ripple delay. An asynchronous mod-11 up-counter uses 4 negative-edge JK flip-flops (J=K=1) and a NAND gate detecting Q3Q1Q0=111 (state 11, 1011) to clear all flip-flops, resetting after 10. ## Answer #### Ripple counter A **ripple counter** is an asynchronous counter in which only the first flip-flop is driven by the external clock and each following flip-flop is clocked by the output of the previous one. The change of state "ripples" through the chain, one flip-flop after another. #### Design: asynchronous mod-11 up counter 1. **Number of flip-flops:** a mod-11 counter needs 11 states (0 to 10). $2^3 = 8 < 11 \le 2^4 = 16$, so 4 flip-flops are needed. JK flip-flops with $J = K = 1$ (toggle) and negative-edge clocks are used. 2. **Clocking:** CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3. With falling-edge triggering, using Q as the next clock gives an up count. 3. **Reset logic:** the counter should go from 10 (1010) back to 0. So it must be cleared as soon as it reaches 11 = **1011**. In 1011, $Q_3 = Q_1 = Q_0 = 1$. In the states 0 to 10, these three bits are never all 1, so a 3-input NAND gate of $Q_3, Q_1, Q_0$ drives the active-low CLEAR of all flip-flops. $$ \overline{CLR} = \overline{Q_3\,Q_1\,Q_0} $$ **Circuit diagram** ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | Q1 ---| NAND |o--> CLR of all FFs (active low) Q0 ---| | ``` **Count table** | Clock | Q3 Q2 Q1 Q0 | Count | |---|---|---| | 0 | 0000 | 0 | | 1–7 | 0001 … 0111 | 1–7 | | 8 | 1000 | 8 | | 9 | 1001 | 9 | | 10 | 1010 | 10 | | 11 | 1011 → 0000 | 0 (cleared) | **Operation:** each falling clock edge toggles FF0, and each stage toggles when the previous output falls 1→0, so the count increases by one per pulse. On the 11th pulse the state 1011 appears for a moment, the NAND output becomes 0, all flip-flops clear, and the count restarts from 0000. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾|___ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_______ Cnt 0 1 2 3 4 5 6 7 8 9 10 0 ``` $Q_3$ is high for counts 8, 9 and 10, so the output frequency at $Q_3$ is $f_{clk}/11$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a ripple counter? A. A counter where all flip-flops share the same clock B. An asynchronous counter where only the first flip-flop gets the external clock and each next one is clocked by the previous output C. A counter that counts only down D. A counter built only from gates Answer: B. In a ripple counter the change of state ripples through the chain of flip-flops. (Key point: Ripple counter definition) 2. The mod-11 counter counts 0 to 10. At which state is it cleared? A. 1010 (10) B. 1011 (11) C. 1100 (12) D. 1111 (15) Answer: B. State 10 must be kept, so the counter is cleared when 11 (1011) appears. (Key point: Reset state) 3. Which gate drives the CLEAR inputs? A. 2-input NAND of Q3 and Q1 B. 3-input NAND of Q3, Q1, Q0 C. 3-input AND of Q3, Q2, Q0 D. 4-input NAND of all outputs Answer: B. Q3, Q1 and Q0 are all 1 only in 1011 (among states 0 to 11), so NAND(Q3,Q1,Q0) clears all flip-flops. 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