--- title: "Comb vs seq; asynchronous mod-12 counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod12-comb-seq" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-comb-seq site: BCT Engineering --- # Comb vs seq; asynchronous mod-12 counter Digital Logic · Chapter 8: Counters - Asked in: 2079 Baisakh, 2+4 marks - Video: [MOD-6 Asynchronous Counter Using JK Flip Flop | Sequential Logic Circuits | Digital Circuit Design](https://www.youtube.com/watch?v=Aka_1pthirk) — Ekeeda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-comb-seq - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Differentiate between combinational and sequential circuits. Explain the operation of asynchronous mod-12 counter with timing diagrams. ## Short answer Combinational circuits: output depends only on present inputs, no memory. Sequential circuits: output depends on inputs and past state, have memory. Asynchronous mod-12 counter: 4 JK flip-flops with J=K=1, NAND of Q3 and Q2 clear at 1100, counting 0-11 and reset on 12th pulse. ## Answer #### Combinational vs sequential circuits | Point | Combinational circuit | Sequential circuit | |---|---|---| | Output depends on | Present inputs only | Present inputs and past state | | Memory | No memory | Has memory (flip-flops/latches) | | Feedback | No feedback path | Feedback from output to input | | Clock | Not needed | Usually clocked | | Analysis tool | Truth table | State table / state diagram | | Examples | Adder, MUX, decoder | Flip-flop, register, counter | #### Asynchronous mod-12 counter A mod-12 ripple counter counts 0 to 11 and returns to 0 on the 12th clock pulse. Four negative-edge JK flip-flops ($2^4 = 16 \ge 12$) are used with $J = K = 1$. CLK drives FF0, and $Q_0$, $Q_1$, $Q_2$ clock FF1, FF2, FF3. The counter must be cleared at 12 = **1100**. It is the first count with $Q_3 = Q_2 = 1$, so a 2-input NAND of $Q_3$ and $Q_2$ drives the active-low CLEAR of all flip-flops. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q2 ---| | ``` **Operation:** FF0 toggles on every falling clock edge; each later flip-flop toggles when the previous Q falls 1→0, so the count goes 0000, 0001, …, 1011. At the 12th pulse the counter momentarily reaches 1100, the NAND output goes low and all flip-flops clear to 0000. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 10 11 0 ``` $Q_3$ is high for counts 8 to 11, so $f_{Q_3} = f_{clk}/12$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the main difference between combinational and sequential circuits? A. Combinational output depends only on present inputs; sequential also depends on past state and has memory B. Combinational circuits have memory; sequential do not C. Sequential circuits never use clocks D. Combinational circuits always use feedback Answer: A. Combinational circuits have no memory; sequential circuits store state with flip-flops or latches. (Key point: Combinational vs sequential) 2. At which state is the mod-12 ripple counter cleared and by what? A. 1011, by NAND of Q3, Q1, Q0 B. 1100, by NAND of Q3 and Q2 C. 1010, by NAND of Q3 and Q1 D. 1111, by AND of all outputs Answer: B. 12 = 1100 is the first state with Q3 = Q2 = 1, so NAND(Q3,Q2) drives the active-low CLEAR. (Key point: Reset state and gate) 3. What is the frequency of Q3 in the mod-12 counter? A. f_clk/8 B. f_clk/12 C. f_clk/16 D. f_clk/6 Answer: B. The counter repeats every 12 pulses, so Q3 has frequency f_clk/12. (Key point: Frequency division) ## Close variants set in other exams - [Comb vs seq; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-comb-seq) — Digital Logic, chapter 8, asked 4× - [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3× ## Related in Digital Logic - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [Comb vs seq; synchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-decade-comb-seq) — Digital Logic, chapter 8, asked 2× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6