--- title: "Synchronous circuits; asynchronous mod-12 counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod12-define-sync" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-define-sync site: BCT Engineering --- # Synchronous circuits; asynchronous mod-12 counter Digital Logic · Chapter 8: Counters - Asked in: 2075 Asoj, 1+5 marks - Video: [U3L6.5 | Mod-12 Asynchronous Counter | Design Mod 12 ripple counter JK flip flop](https://www.youtube.com/watch?v=o9wWknyNRdI) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-define-sync - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Define synchronous sequential circuits. Explain the operation of asynchronous mod-12 counter with necessary diagrams. ## Short answer A synchronous sequential circuit has all flip-flops driven by a common clock. An asynchronous mod-12 counter uses four JK flip-flops (J=K=1) with Q outputs clocking the next stage. It counts 0–11; when state 1100 appears, a NAND gate of Q3 and Q2 clears all flip-flops to 0000, resetting after 12 pulses. ## Answer #### Synchronous sequential circuit A **synchronous sequential circuit** is a sequential circuit in which all flip-flops are driven by a common clock, so the state can change only at the active clock edge. Examples: synchronous counters, shift registers, sequence detectors. #### Asynchronous mod-12 counter It counts 0 to 11 (0000 to 1011) and returns to 0 on the 12th clock pulse. **Construction** - 4 negative-edge JK flip-flops ($2^4 = 16 \ge 12$), $J = K = 1$. - CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3. - Count 12 = **1100** is the first state with $Q_3 = Q_2 = 1$. A NAND gate of $Q_3$ and $Q_2$ drives the active-low CLEAR of all flip-flops. ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q2 ---| | ``` **Operation** 1. FF0 toggles on every falling edge; each later stage toggles when the previous Q falls 1→0, so the count rises 0, 1, 2, …, 11. 2. On the 12th pulse the outputs go from 1011 towards 1100. As soon as $Q_3 = Q_2 = 1$, the NAND output goes low and clears all flip-flops to 0000. State 1100 lasts only a few nanoseconds. | Clock | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---| | Q3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | | Q2 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | | Q1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | | Q0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 8 9 10 11 0 ``` $Q_3$ is high for counts 8–11, so it is a divide-by-12 output. IC 7492 is a commercial divide-by-12 ripple counter. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is true of a synchronous sequential circuit? A. Flip-flops are driven by a common clock and state changes only at the active edge B. Each flip-flop has its own clock C. State changes whenever inputs change D. It contains no flip-flops Answer: A. A common clock makes the state change only at the active edge, so the behaviour is predictable. (Key point: Synchronous sequential circuit) 2. Why is a NAND gate of Q3 and Q2 used for the mod-12 asynchronous counter? A. 1100 (12) is the first state with Q3 = Q2 = 1, so it triggers the clear B. 1011 is the first state with Q3 = Q2 = 1 C. 1010 has Q3 = Q2 = 1 D. Q3 and Q2 are both 1 for every valid count Answer: A. Counts 0 to 11 never have both Q3 and Q2 high; 12 = 1100 is the first, so NAND goes low and clears all flip-flops. (Key point: Reset state for mod-12) 3. How is the NAND output connected to the flip-flops? A. To the clock input of FF0 B. To the active-low CLEAR of all flip-flops C. To the J inputs D. To the active-low CLEAR of FF3 only Answer: B. The NAND output goes low at 1100 and asynchronously clears all four flip-flops to 0000. (Key point: Clear type) 4. How long does state 1100 last in the asynchronous mod-12 counter? A. A full clock period B. Only a few nanoseconds, until the clear takes effect C. Half a clock period D. It is a stable counted state Answer: B. The clear acts almost immediately, so 1100 is a brief transient, not one of the 12 stable states. (Key point: Duration of state 12) ## Close variants set in other exams - [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3× ## Related in Digital Logic - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 - [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2× ## Related in other subjects - [Multiplexing; synchronous vs asynchronous TDM](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Amux-compare-sync-async-tdm) — Data Communication, chapter 6, asked 6×