--- title: "Asynchronous mod-12 down counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod12-down-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-down-counter site: BCT Engineering --- # Asynchronous mod-12 down counter Digital Logic · Chapter 8: Counters - Asked in: 2076 Chaitra, 2+6 marks - Video: [U3L6.5 | Mod-12 Asynchronous Counter | Design Mod 12 ripple counter JK flip flop](https://www.youtube.com/watch?v=o9wWknyNRdI) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-down-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Differentiate between combinational and sequential logic circuits. Construct and explain mod-12 asynchronous down counter with negative edge clock triggering system. Use JK flip-flops and necessary logic gates. ## Short answer Combinational circuits depend only on present inputs; sequential circuits have memory and feedback. A mod-12 asynchronous down counter uses four negative-edge JK flip-flops (J=K=1) clocked from Q' of the previous stage. It counts 15 down to 4; when Q3=Q2=0 (state 0011), an OR gate presets all flip-flops to 1111, giving modulo 12. ## Answer #### Combinational vs sequential logic circuits | Point | Combinational circuit | Sequential circuit | |---|---|---| | Output depends on | Present inputs only | Present inputs and past state | | Memory | No memory | Has memory (flip-flops/latches) | | Feedback | No feedback path | Feedback from output to input | | Clock | Not needed | Usually clocked | | Analysis tool | Truth table | State table / state diagram | | Examples | Adder, MUX, decoder | Flip-flop, register, counter | #### Mod-12 asynchronous down counter (negative-edge JK) **Design idea** 1. 12 states need 4 flip-flops ($2^4 = 16 \ge 12$). JK flip-flops with $J = K = 1$ toggle on each falling clock edge. 2. **Down counting with negative-edge clocks:** a stage must toggle when the previous output goes $0 \to 1$, i.e. when its $\overline{Q}$ goes $1 \to 0$. So FF0 gets CLK, and $\overline{Q_0}$, $\overline{Q_1}$, $\overline{Q_2}$ drive the clocks of FF1, FF2, FF3. 3. **Truncating to 12 states:** a natural 4-bit down counter counts 15, 14, …, 0. We keep the 12 states **1111 (15) down to 0100 (4)**. When the count falls from 0100 to **0011**, the counter is preset at once to 1111. 4. **Preset logic:** 0011 is the only state reached in which $Q_3 = Q_2 = 0$ (the ripple transients of the other steps never make both 0). An OR gate gives $Q_3 + Q_2 = 0$ only then, and its output drives the active-low PRESET of all four flip-flops: $$ \overline{PR} = Q_3 + Q_2 $$ (If the count 11 → 0 is chosen instead, the reset state 1111 must be decoded, but 1111 also appears as a ripple transient when the count goes from 1000 to 0111, which would cause a false load. The 15 → 4 sequence avoids this.) **Circuit diagram** ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3 +-----+ +-----+ +-----+ +-----+ (count is read from Q3 Q2 Q1 Q0; each FF has an active-low PRESET input) Q3 ---| | | OR |----> PRESET of all FFs (active low) Q2 ---| | ``` **Count sequence** | Clock | Q3 Q2 Q1 Q0 | State | |---|---|---| | 0 | 1111 | 15 | | 1 | 1110 | 14 | | 2 | 1101 | 13 | | … | … | … | | 10 | 0101 | 5 | | 11 | 0100 | 4 | | 12 | 0011 → 1111 | preset to 15 | **Operation:** each falling clock edge toggles FF0. When $Q_0$ rises (0→1), $\overline{Q_0}$ falls and FF1 toggles, and so on, so the count decreases by one per pulse. After the 12th pulse the counter tries to enter 0011; the OR output goes low and presets all flip-flops to 1111, starting a new cycle of 12 states. **Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾ Q2 ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾ Q1 ‾‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾ Q0 ‾‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾ Cnt 15 14 13 12 11 10 9 8 7 6 5 4 15 ``` $Q_3$ completes one cycle every 12 clock pulses ($f_{clk}/12$). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the main difference between combinational and sequential circuits? A. Combinational output depends on present and past inputs; sequential on present inputs only B. Combinational output depends on present inputs only; sequential also depends on past state (has memory) C. Both have memory but only sequential uses a clock D. Combinational circuits use flip-flops; sequential use gates Answer: B. Combinational circuits have no memory; sequential circuits store past state in flip-flops or latches. (Key point: Combinational vs sequential) 2. For a negative-edge JK down counter, what clocks FF1, FF2 and FF3? A. Q0, Q1, Q2 B. Q0', Q1', Q2' (the complemented outputs) C. CLK directly D. Q3 for all Answer: B. A stage must toggle when the lower bit goes 0 to 1, which is a falling edge of Q'; so Q' outputs drive the next clocks. (Key point: Clocking a down counter) 3. Which 12 states does the counter keep, and when is the preset triggered? A. 15 down to 4; preset when the count would enter 0011 B. 11 down to 0; preset when it reaches 1111 C. 15 down to 4; preset when Q3Q2 = 11 D. 12 down to 1; preset at 0000 Answer: A. States 1111 to 0100 are kept. On entering 0011, Q3 = Q2 = 0 and the OR output goes low, presetting to 1111. (Key point: Truncation to 12 states) 4. Why is PR' = Q3 + Q2 used instead of decoding the reset state 1111? A. OR gates are faster than NAND gates B. 1111 also appears as a ripple transient from 1000 to 0111 and would give a false load C. 1111 can never occur in a down counter D. Active-low preset cannot be driven by a NAND gate Answer: B. Decoding 1111 would falsely trigger on the transient during 1000 to 0111. The 15 to 4 sequence with Q3 + Q2 avoids this. (Key point: Preset logic) ## Related in Digital Logic - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 - [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8 - [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4× ## Related in other subjects - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×