--- title: "Asynchronous mod-12 up counter using JK" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod12-up-jk" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-up-jk site: BCT Engineering --- # Asynchronous mod-12 up counter using JK Digital Logic · Chapter 8: Counters - Asked in: 2081 Bhadra, 6 marks - Video: [U3L6.5 | Mod-12 Asynchronous Counter | Design Mod 12 ripple counter JK flip flop](https://www.youtube.com/watch?v=o9wWknyNRdI) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-up-jk - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Build the design of an asynchronous mod-12 up-counter with positive edge triggering clock and use JK flip-flops. ## Short answer Use four positive-edge JK flip-flops with J=K=1. Clock FF0 from CLK; clock FF1, FF2, FF3 from Q0', Q1', Q2'. A NAND of Q3 and Q2 drives active-low clear to reset at count 12 (1100), so the counter cycles 0–11. ## Answer An **asynchronous mod-12 up counter** counts 0 to 11 and returns to 0 on the 12th clock pulse. Only FF0 is driven by the clock; the other flip-flops are driven by the previous stage. #### Design steps 1. **Flip-flops:** $2^4 = 16 \ge 12$, so 4 JK flip-flops, all with $J = K = 1$ (toggle mode). 2. **Clocking for positive-edge flip-flops:** in an up count a stage must toggle when the previous output falls 1→0. A falling $Q$ is a rising $\overline{Q}$, so with **positive-edge** triggering each stage is clocked from the $\overline{Q}$ of the previous stage: CLK → FF0, $\overline{Q_0}$ → FF1, $\overline{Q_1}$ → FF2, $\overline{Q_2}$ → FF3. 3. **Reset logic:** count 12 = **1100** must clear the counter. It is the first state with $Q_3 = Q_2 = 1$, so $$ \overline{CLR} = \overline{Q_3\,Q_2} $$ A 2-input NAND gate feeds the active-low CLEAR of all four flip-flops. #### Circuit diagram ```text J=K=1 J=K=1 J=K=1 J=K=1 +-----+ +-----+ +-----+ +-----+ CLK-> FF0 |Q0'-> FF1 |Q1'-> FF2 |Q2'-> FF3 |Q3 +--o--+ +--o--+ +--o--+ +--o--+ CLR CLR CLR CLR Q3 ---| | | NAND |o--> CLR of all FFs (active low) Q2 ---| | ``` (">" marks a positive-edge clock input; the count is read from $Q_3Q_2Q_1Q_0$.) #### Count sequence | Clock | Q3 Q2 Q1 Q0 | Count | |---|---|---| | 0 | 0000 | 0 | | 1 | 0001 | 1 | | 4 | 0100 | 4 | | 8 | 1000 | 8 | | 11 | 1011 | 11 | | 12 | 1100 → 0000 | 0 | #### Operation and timing FF0 toggles at every rising clock edge. When $Q_0$ falls, $\overline{Q_0}$ rises and toggles FF1, and so on, giving an up count. On the 12th rising edge the counter reaches 1100, the NAND output goes low and clears all flip-flops to 0000. ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q3 ______________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____ Q2 ______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________ Q1 ______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_____ Q0 __|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_____ Cnt 0 1 2 3 4 5 6 7 8 9 10 11 0 ``` $Q_3$ is high for counts 8–11, so it gives $f_{clk}/12$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why are 4 JK flip-flops used for the asynchronous mod-12 counter? A. Because 2^3 = 8 < 12 and 2^4 = 16 >= 12 B. Because 12 has 4 factors C. Because each count needs its own flip-flop D. Because JK flip-flops come in groups of four Answer: A. n flip-flops give 2^n states; 3 give only 8, so 4 are the minimum, with J = K = 1 for toggling. (Key point: Number of flip-flops) 2. In an up counter built with positive-edge JK flip-flops, how is each later stage clocked? A. From Q of the previous stage B. From the common clock C. From Q-bar of the previous stage D. From the NAND reset output Answer: C. A stage must toggle when the previous Q falls, which is a rising Q-bar, so a positive-edge FF is clocked from the previous Q-bar. (Key point: Clocking positive-edge FFs) 3. Which gate resets the counter at count 12 (1100)? A. NAND of Q3 and Q2 driving active-low CLEAR B. AND of Q1 and Q0 driving PRESET C. NOR of Q3 and Q2 driving CLEAR D. NAND of Q3 and Q0 driving CLEAR Answer: A. 1100 is the first state with Q3 = Q2 = 1, so NAND(Q3,Q2) goes low and clears all flip-flops. (Key point: Reset condition) 4. What frequency does Q3 give for a mod-12 counter? A. f_clk/8 B. f_clk/16 C. f_clk/6 D. f_clk/12 Answer: D. Q3 completes one cycle every 12 clock pulses, so it gives f_clk/12. (Key point: Output frequency) ## Related in Digital Logic - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8 - [Ripple counter; asynchronous mod-11 up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod11-up-counter) — Digital Logic, chapter 8 - [Mod-10 negative edge ripple counter with JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-ripple-jk-negative-edge) — Digital Logic, chapter 8 - [Mod-5 Gray code synchronous up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-gray-sync-counter) — Digital Logic, chapter 8