--- title: "Asynchronous mod-12 up counter, positive edge" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-mod12-up-t-positive" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-up-t-positive site: BCT Engineering --- # Asynchronous mod-12 up counter, positive edge Digital Logic · Chapter 8: Counters - Asked in: 2082 Baisakh, 5 marks; 2078 Kartik, 7 marks; 2076 Asoj, 5 marks (asked 3 times) - Video: [MOD 12 Ripple up Counter Using T flip flop | Wave form for MOD 12 asynchronous counter](https://www.youtube.com/watch?v=JYpPqyHmH4Q) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-mod12-up-t-positive - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Construct asynchronous T flip-flopped mod-12 up-counter and use positive edge triggered clock. ## Short answer Use four T flip-flops with T = 1. Clock FF0 directly, FF1 from Q0', FF2 from Q1', FF3 from Q2'. Detect state 1100 (12) with a NAND gate to clear all flip-flops, giving a modulo-12 up counter (0-11). ## Answer A **mod-12 asynchronous (ripple) up counter** counts 0 to 11 (0000 to 1011) and then resets to 0000. Since $2^3 < 12 \le 2^4$, **4 T flip-flops** are needed. Each flip-flop has T = 1, so it toggles at every active clock edge it receives. #### Clock connections for positive edge triggering In an up counter, a flip-flop must toggle when the previous output goes **1 to 0**. With positive (rising) edge triggered flip-flops, this 1-to-0 change of Q is the same instant as the 0-to-1 change of $\overline{Q}$. So: - FF0 is clocked by the external CLK. - FF1 is clocked by $\overline{Q_0}$, FF2 by $\overline{Q_1}$, FF3 by $\overline{Q_2}$. #### Reset logic The count must stop at 11, so the first unwanted state 12 = **1100** is detected. In 1100 only Q3 and Q2 are 1 (and no earlier count 0 to 11 has both Q3 and Q2 = 1), so $$ \overline{CLR} = \overline{Q_3 Q_2} $$ A 2-input NAND gate drives the active-low CLEAR inputs of all flip-flops. As soon as 1100 appears, the NAND output goes 0 and all flip-flops clear to 0000 (state 1100 exists only for a few ns). #### Circuit ```text T=1 T=1 T=1 T=1 +------+ +------+ +------+ +------+ CLK>|> FF0 | +-->|> FF1 | +-->|> FF2 | +-->|> FF3 | | Q0'|-+ | Q1'|-+ | Q2'|-+ | | | CLR' | | CLR' | | CLR' | | CLR' | +------+ +------+ +------+ +------+ Outputs: Q0 (LSB), Q1, Q2, Q3 (MSB) Q3 --+ +-->[NAND]--> CLR' of all four flip-flops Q2 --+ ``` #### Count sequence | CLK | Q3 | Q2 | Q1 | Q0 | Count | |---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 1 | | 2 | 0 | 0 | 1 | 0 | 2 | | 3 | 0 | 0 | 1 | 1 | 3 | | 4 | 0 | 1 | 0 | 0 | 4 | | 5 | 0 | 1 | 0 | 1 | 5 | | 6 | 0 | 1 | 1 | 0 | 6 | | 7 | 0 | 1 | 1 | 1 | 7 | | 8 | 1 | 0 | 0 | 0 | 8 | | 9 | 1 | 0 | 0 | 1 | 9 | | 10 | 1 | 0 | 1 | 0 | 10 | | 11 | 1 | 0 | 1 | 1 | 11 | | 12 | 0 | 0 | 0 | 0 | 0 | At the 12th clock the counter reaches 1100 for a moment and is immediately cleared to 0000. #### Timing diagram ```text 1 2 3 4 5 6 7 8 9 10 11 12 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| Q0 _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|__ Q1 _____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|__ Q2 _____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__________________ Q3 _____________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__ ``` Q0 toggles at every rising edge of CLK; Q1 toggles when Q0 falls; Q2 when Q1 falls; Q3 when Q2 falls. Q3 is high for counts 8 to 11, so Q3 has frequency $f_{CLK}/12$. (In a real ripple counter each change is delayed by one flip-flop delay from the previous stage.) ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many T flip-flops (T = 1) are needed for an asynchronous mod-12 counter? A. 3 B. 4 C. 6 D. 12 Answer: B. 2^3 = 8 < 12 <= 2^4 = 16, so 4 flip-flops are required. (Key point: Flip-flops needed) 2. For an up counter with positive-edge triggered flip-flops, how is FF1 clocked? A. By the external CLK B. By Q0 C. By Q0' (complement of Q0) D. By Q2' Answer: C. FF1 must toggle when Q0 goes 1 to 0, which is the same instant Q0' goes 0 to 1, a rising edge, so Q0' clocks FF1. (Key point: Clocking with positive edge) 3. Which gate and inputs clear the counter when it reaches 12 (1100)? A. 3-input NAND of Q3, Q2, Q1 B. 2-input NAND of Q3 and Q2 C. 2-input AND of Q3 and Q0 D. 2-input NAND of Q3 and Q1 Answer: B. 1100 is the first state with Q3 = Q2 = 1, so NAND(Q3, Q2) drives the active-low CLEAR of all flip-flops. (Key point: Reset detection) 4. What is the frequency of Q3 in this mod-12 counter? A. f_CLK/8 B. f_CLK/16 C. f_CLK/12 D. f_CLK/4 Answer: C. The counter repeats every 12 clocks, so Q3 has frequency f_CLK/12. (Key point: Output frequency) ## Related in Digital Logic - [Asynchronous mod-12 up counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-jk) — Digital Logic, chapter 8 - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Ripple counter; asynchronous mod-11 up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod11-up-counter) — Digital Logic, chapter 8 - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× - [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4× ## Related in other subjects - [Edge triggered D flip-flop with preset, clear](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ad-flip-flop-edge-triggered) — Basic Electronics Engineering, chapter 6