--- title: "3-bit asynchronous up/down counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:async-up-down-counter-3bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/async-up-down-counter-3bit site: BCT Engineering --- # 3-bit asynchronous up/down counter Digital Logic · Chapter 8: Counters - Asked in: 2078 Bhadra, 6 marks; 2074 Chaitra, 6 marks (asked 2 times) - Video: [3 Bit & 4 Bit UP/DOWN Ripple Counter](https://www.youtube.com/watch?v=5Um3NDvsYjQ) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/async-up-down-counter-3bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question Explain the operation of 3 bit Asynchronous up/down counter with timing diagram. ## Short answer Use negative-edge JK flip-flops with J=K=1. For up counting (M=1) clock each stage from Q of the previous; for down counting (M=0) clock from Q'. Mode M selects the clock source through AND-OR gates. ## Answer An **asynchronous up/down counter** is a ripple counter that can count either upward (0, 1, 2, …, 7) or downward (7, 6, …, 0) depending on a **mode control input M**. Only the first flip-flop gets the external clock; each later flip-flop is clocked by the previous stage. #### Principle For negative-edge triggered JK flip-flops with $J = K = 1$ (toggle mode): - **Up count:** the next flip-flop must toggle when the previous output goes $1 \to 0$, so it is clocked from $Q$. - **Down count:** the next flip-flop must toggle when the previous output goes $0 \to 1$, i.e. when $\overline{Q}$ goes $1 \to 0$, so it is clocked from $\overline{Q}$. A 2-input AND-OR (or MUX) between stages selects $Q$ or $\overline{Q}$: $$ CLK_1 = M\,Q_0 + \overline{M}\,\overline{Q_0}, \qquad CLK_2 = M\,Q_1 + \overline{M}\,\overline{Q_1} $$ M = 1 gives up counting, M = 0 gives down counting. #### Circuit ```text M=1: UP M=0: DOWN (all J = K = 1) +-----+ Q0 --[AND]--+ CLK --o| FF0 | M +--[OR]--> CLK of FF1 +-----+ Q0' --[AND]--+ M' +-----+ Q1 --[AND]--+ ... -o| FF1 | M +--[OR]--> CLK of FF2 +-----+ Q1' --[AND]--+ M' ``` Outputs $Q_2Q_1Q_0$ (Q0 = LSB) give the count. #### Operation 1. **M = 1 (up):** FF0 toggles on every falling clock edge. When $Q_0$ falls from 1 to 0, FF1 toggles; when $Q_1$ falls, FF2 toggles. Sequence: 000, 001, 010, …, 111, 000. 2. **M = 0 (down):** FF1 toggles when $Q_0$ rises (its $\overline{Q_0}$ falls), and FF2 toggles when $Q_1$ rises. Sequence: 000, 111, 110, …, 001, 000. #### Timing diagram: up mode (M = 1) ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___ Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 1 2 3 4 5 6 7 0 ``` #### Timing diagram: down mode (M = 0) ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q2 ____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________ Q1 ____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___ Cnt 0 7 6 5 4 3 2 1 0 ``` #### Points to note - Each stage waits for the previous one, so the total delay is $3\,t_{pd}$ and short false states appear during transitions. - The mode M should be changed only when the clock is steady; switching M can create an extra edge at the next stage and give a wrong count. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. For negative-edge JK flip-flops in up counting, how is the next stage clocked? A. From Q of the previous stage B. From Q' of the previous stage C. From the external clock D. From the mode input M Answer: A. In up counting the next stage toggles when the previous output falls 1 to 0, which a negative-edge FF sees on Q. (Key point: Up mode clocking) 2. Why is Q' used to clock the next stage in down mode? A. Because Q' is always slower B. To avoid using the clock C. Because the next stage must toggle when the previous Q goes 0 to 1, i.e. Q' goes 1 to 0 D. Because the J and K inputs become 0 Answer: C. In down counting the next stage toggles when the previous Q rises, which is a falling edge of Q'. (Key point: Down mode clocking) 3. What do CLK1 = M Q0 + M' Q0' and the AND-OR gate do? A. M = 1 selects Q (up count); M = 0 selects Q' (down count) B. M = 1 selects Q' (up count); M = 0 selects Q (down count) C. They disable FF1 when M = 1 D. They reset the counter when M changes Answer: A. M = 1 passes Q for up counting and M = 0 passes Q' for down counting. (Key point: Mode selection) 4. Which is a limitation noted for the asynchronous up/down counter? A. Delays add up to 3 t_pd and M should be changed only when the clock is steady B. It cannot count down below 4 C. It needs J = K = 0 D. All flip-flops change simultaneously so there are no false states Answer: A. Each stage waits for the previous one, so false states appear, and switching M can create an extra clock edge. (Key point: Ripple delay and mode change) ## Related in Digital Logic - [4-bit asynchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-down-counter-4bit) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8 - [Asynchronous mod-12 down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-down-counter) — Digital Logic, chapter 8 - [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8 - [Asynchronous mod-12 up counter, positive edge](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-up-t-positive) — Digital Logic, chapter 8, asked 3× - [Ripple counter; asynchronous mod-11 up counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod11-up-counter) — Digital Logic, chapter 8 ## Related in other subjects - [Structural modelling; 3-bit up counter](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-structural-3bit-counter) — Embedded System, chapter 9 - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Count up/down and tracking type ADC](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acount-up-down-tracking-adc) — Advanced Electronics, chapter 3