--- title: "Problems in asynchronous sequential design" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:asynchronous-sequential-problems" source: https://www.bctengineer.com/q/semester_3/digital_logic/asynchronous-sequential-problems site: BCT Engineering --- # Problems in asynchronous sequential design Digital Logic · Chapter 9: Sequential Machines - Asked in: 2068 Baisakh, 6 marks - Video: [Problems in Asynchronous Sequential Logic Design](https://www.youtube.com/watch?v=XBfz3A4RCMk) — Impactful Engineers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/asynchronous-sequential-problems - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question With an example, state and explain the problems associated in the design of asynchronous sequential circuit. ## Short answer Races occur when state variables change at different times; critical races may settle into a wrong stable state. Hazards produce glitches that can propagate through feedback and cause incorrect transitions. Cycles may lead to oscillation. Designs must operate in fundamental mode with race-free state assignments. ## Answer An **asynchronous sequential circuit** has no clock: its state (held in feedback loops through gate delays) changes as soon as an input changes. This makes it fast, but the design has several problems that clocked circuits avoid. #### 1. Races A race happens when **two or more state variables must change** in one transition. Due to unequal delays they do not change together, so the circuit passes through an intermediate state. - **Non-critical race:** the circuit still reaches the correct final state whatever order the variables change in. - **Critical race:** the final stable state depends on which variable changes first, so the circuit may settle in a **wrong state**. **Example:** state $y_1 y_2$ must go from 00 to 11. If $y_1$ changes first the circuit passes 10; if $y_2$ first, it passes 01. If, for the present input, 01 is a stable state, the circuit stops at 01 instead of 11 — a critical race. ```text 00 ---> 11 intended 00 ---> 10 ---> 11 (y1 first, OK) 00 ---> 01 (stable) stuck (y2 first, error) ``` Remedy: choose a **race-free state assignment** (adjacent codes differing in one bit), add extra states, or use a one-hot code. #### 2. Cycles The circuit may go through a sequence of unstable states before reaching a stable one. If no stable state exists in that column, it keeps **oscillating** (an unending cycle) between states. #### 3. Hazards Unequal gate delays give momentary wrong outputs (glitches): - **Static-1 hazard:** output should stay 1 but drops to 0 briefly, e.g. $F = AB + A'C$ when A changes with B = C = 1. Fixed by adding the consensus term $BC$. - **Static-0 hazard:** output should stay 0 but rises to 1 briefly. **Dynamic hazard:** output should change once but changes several times (e.g. 1 → 0 → 1 → 0) before settling. - **Essential hazard:** caused by an input change reaching different parts of the circuit at different times; removed by adding delay in the feedback. Because the feedback loops carry these glitches back to the inputs, a hazard can push the circuit into a wrong stable state. #### 4. Other restrictions - **Fundamental mode:** only one input may change at a time, and only after the circuit is stable. - Analysis and design are harder (flow table, merging of rows, state assignment), and the circuit is sensitive to temperature and delay variations. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is a critical race? A. Two or more state variables must change and the final state depends on which changes first B. Two state variables change together and the circuit always reaches the right state C. A glitch on the output D. An input changing twice in a row Answer: A. In a critical race unequal delays make the final stable state depend on the order of change, so it may be wrong. (Key point: Critical race) 2. How are races avoided? A. Adding more inputs B. Using a race-free state assignment where adjacent codes differ in one bit C. Changing several inputs at once D. Removing feedback delay Answer: B. A race-free assignment (or extra states, or one-hot) means only one variable changes per transition. (Key point: Race remedy) 3. How is the static-1 hazard in F = AB + A'C (B = C = 1, A changing) removed? A. Adding the term AC B. Removing the term A'C C. Adding the consensus term BC D. Adding a clock Answer: C. The consensus term BC holds the output at 1 while A changes. (Key point: Static-1 hazard) 4. What does the fundamental-mode restriction require? A. The clock must be slow B. All inputs change together C. Outputs are sampled on the clock edge D. Only one input changes at a time, and only after the circuit is stable Answer: D. Fundamental mode allows a single input change at a time, after the circuit has settled. (Key point: Fundamental mode) ## Related in Digital Logic - [Two-input sequential circuit using T](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Atwo-input-sequential-circuit-t) — Digital Logic, chapter 9 - [Hazards in asynchronous design; 2-bit comparator](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ahazards-2bit-comparator) — Digital Logic, chapter 4 - [Synchronous circuits; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-counter-define) — Digital Logic, chapter 8, asked 2× - [Comb vs seq; asynchronous decade counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-decade-comb-seq) — Digital Logic, chapter 8, asked 4× - [Comb vs seq; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-comb-seq) — Digital Logic, chapter 8, asked 3× - [Synchronous circuits; asynchronous mod-12 counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-mod12-define-sync) — Digital Logic, chapter 8, asked 2× ## Related in other subjects - [Design and construction problems of hill roads](https://www.bctengineer.com/question.md?key=semester_6%2Ftransportation_engineering_i%3Ahill-problems) — Transportation Engineering I, chapter 5, asked 11× - [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6 - [Design: 250 m head plant, 66 kV double circuit](https://www.bctengineer.com/question.md?key=semester_8%2Fpower_plant_design%3Adesign-2071-250m-0-92mh) — Power Plant Design, chapter 4, asked 13× - [Establishing requirements for circuit design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Areq-to-design) — Instrumentation II, chapter 7, asked 4×