--- title: "BCD-to-7-segment decoder; frequency counter" subject: "Digital Logic" chapter: 11 key: "semester_3/digital_logic:bcd-7segment-frequency-counter" source: https://www.bctengineer.com/q/semester_3/digital_logic/bcd-7segment-frequency-counter site: BCT Engineering --- # BCD-to-7-segment decoder; frequency counter Digital Logic · Chapter 11: Applications - Asked in: 2082 Shrawan, 2+5 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/bcd-7segment-frequency-counter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-11 ## Question What is a BCD-to 7 segment display decoder? Explain the frequency counter with necessary diagrams. ## Short answer A BCD-to-7-segment decoder converts 4‑bit BCD to segment outputs a–g (IC 7447/7448). A frequency counter counts input cycles during a precise gate time Tg from a crystal divider. A Schmitt trigger shapes the input; an AND gate passes pulses while gate is open; decade counters, latch, and decoder/display show N, f = N / Tg, e.g., 0.1 s gate, 4567 counts → 45.67 kHz. ## Answer #### BCD-to-7-segment decoder A **BCD-to-7-segment decoder** is a combinational circuit that converts a 4-bit BCD input (DCBA = 0000 to 1001) into the seven outputs a–g needed to light the segments of a 7-segment display, so that the decimal digit 0–9 appears. Example: input 0101 (5) makes segments a, f, g, c, d active. The **7447** (active-LOW outputs, for common-anode displays) and **7448** (active-HIGH, for common-cathode) are common ICs. ```text a ───── f | | b DCBA ─> [7447] ─> a b c d e f g | g | ───── e | | c | | ───── d ``` #### Frequency counter A **frequency counter** measures the frequency of a signal by counting how many cycles of the signal occur during an accurately known gate time. If $N$ cycles are counted in gate time $T_g$: $$ f = \frac{N}{T_g} $$ With $T_g = 1$ s, the count $N$ is directly the frequency in Hz. ```text Input ─> Amplifier + Schmitt ──────┐ v Crystal ─> Time-base ─> Gate ─> ┌─────┐ osc. divider control │ AND │ │ │ └──┬──┘ │ │ v │ └─> Decade counters │ reset │ │ v └──────> Latch (strobe) v BCD-to-7-seg decoders v 7-segment display ``` **Blocks and operation** 1. **Input shaper** – an amplifier and Schmitt trigger convert the unknown input (sine, triangle, etc.) into clean rectangular pulses, one per cycle. 2. **Crystal oscillator and time-base divider** – a stable oscillator (e.g. 1 MHz) is divided by decade counters to give accurate gate times such as 1 s, 0.1 s or 10 ms. 3. **Gate control flip-flop** – produces a gate pulse of exactly $T_g$ width. 4. **Main AND gate** – passes input pulses to the counters only during $T_g$. 5. **Decade counters (e.g. 7490)** – count the pulses in BCD. 6. **Latch** – at the end of the gate time a strobe pulse copies the count into the latch so the display stays steady; then a reset pulse clears the counters for the next measurement. 7. **BCD-to-7-segment decoders and display** – show the latched count, usually as a multiplexed display. **Example:** with $T_g = 0.1$ s, if 4,567 pulses are counted, $f = 4567 / 0.1 = 45{,}670$ Hz $= 45.67$ kHz. A longer gate time gives better resolution ($\pm 1$ count $= \pm 1/T_g$ Hz) but a slower update. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does a BCD-to-7-segment decoder do? A. Converts a 4-bit BCD input (0-9) into the seven outputs a-g that light the proper segments B. Converts binary into Gray code C. Divides frequency by 10 D. Counts pulses in BCD Answer: A. It is a combinational circuit that drives the segments to show decimal digits 0-9. (Key point: BCD to 7-segment decoder) 2. Which statement about 7447 and 7448 is correct? A. 7447 has active-LOW outputs for common-anode displays; 7448 has active-HIGH outputs for common-cathode B. 7447 is for common-cathode; 7448 for common-anode C. Both have active-HIGH outputs D. Both are counters Answer: A. 7447 outputs are active LOW (common anode), and 7448 outputs are active HIGH (common cathode). (Key point: 7447 vs 7448) 3. What happens at the end of the gate time in the frequency counter? A. A strobe copies the count into the latch, then a reset clears the counters B. The counters are reset, then latched C. The oscillator stops D. The decoder is removed Answer: A. The strobe stores the count so the display is steady, and reset then clears the counters for the next measurement. (Key point: Latch and reset sequence) 4. With T_g = 0.1 s and 4567 pulses counted, what is f? A. 456.7 Hz B. 4567 Hz C. 45,670 Hz D. 456,700 Hz Answer: C. f = N / T_g = 4567 / 0.1 = 45,670 Hz = 45.67 kHz. (Key point: Frequency calculation) ## Related in Digital Logic - [BCD-to-seven-segment decoder, segments a and e](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-seven-segment-a-e) — Digital Logic, chapter 4 - [Seven-segment decoder "b" segment](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ab-segment-seven-segment) — Digital Logic, chapter 4, asked 2× - [DEMUX vs decoder; seven-segment "b" segment](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-decoder-b-segment) — Digital Logic, chapter 4 - [BCD decoder; 1's and 2's complements](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-decoder-complements) — Digital Logic, chapter 4 - [Combinational vs sequential; BCD-to-decimal decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-to-decimal-decoder) — Digital Logic, chapter 4 - [BCD synchronous counter using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-synchronous-counter-t) — Digital Logic, chapter 8 ## Related in other subjects - [BCD counter 0-9999 on seven segment VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-bcd-counter-seven-segment) — Embedded System, chapter 9 - [Seven segment display and clock counter](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aseven-segment-clock-design) — Embedded System, chapter 9 - [Display 0 to 9 on seven segment](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-seven-segment-0-9) — Embedded System, chapter 9, asked 2× - [Display 99 to 00 on seven segment](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-seven-segment-99-00) — Embedded System, chapter 9