---
title: "BCD decoder; 1's and 2's complements"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:bcd-decoder-complements"
source: https://www.bctengineer.com/q/semester_3/digital_logic/bcd-decoder-complements
site: BCT Engineering
---

# BCD decoder; 1's and 2's complements

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2075 Asoj, 3+3 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/bcd-decoder-complements
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Realize the circuit diagram for BCD decoder. Explain 1's and 2's complements with examples?

## Short answer

BCD decoder activates one of ten outputs: D0=A'B'C'D', D1=A'B'C'D, D2=B'CD', D3=B'CD, D4=BC'D', D5=BC'D, D6=BCD', D7=BCD, D8=AD', D9=AD. 1's complement inverts all bits; 2's complement adds 1 to the 1's complement.

## Answer

#### BCD decoder (BCD-to-decimal, 4-to-10)

A **BCD decoder** takes a 4-bit BCD code $ABCD$ ($A$ = MSB) and activates one of ten outputs $D_0$–$D_9$ (IC 7442). Codes 1010–1111 never occur, so they are don't-cares and allow partial decoding.

| Digit | ABCD | Full decoding | Simplified (with don't-cares) |
|---|---|---|---|
| 0 | 0000 | $A'B'C'D'$ | $A'B'C'D'$ |
| 1 | 0001 | $A'B'C'D$ | $A'B'C'D$ |
| 2 | 0010 | $A'B'CD'$ | $B'CD'$ |
| 3 | 0011 | $A'B'CD$ | $B'CD$ |
| 4 | 0100 | $A'BC'D'$ | $BC'D'$ |
| 5 | 0101 | $A'BC'D$ | $BC'D$ |
| 6 | 0110 | $A'BCD'$ | $BCD'$ |
| 7 | 0111 | $A'BCD$ | $BCD$ |
| 8 | 1000 | $AB'C'D'$ | $AD'$ |
| 9 | 1001 | $AB'C'D$ | $AD$ |

```text
 A B C D   A' B' C' D'  (inverters)
 |  |  |  |
 +--+--+--+--[AND]--- D0 = A'B'C'D'
 +--+--+--+--[AND]--- D1 = A'B'C'D
      ...  (one AND gate per output)
 +--------+--[AND]--- D8 = AD'
 +--------+--[AND]--- D9 = AD
```

Ten AND gates and four inverters form the decoder.

#### 1's and 2's complements

**1's complement:** invert every bit (0 → 1, 1 → 0).
Example: 1's complement of $10110$ is $01001$.

**2's complement:** 1's complement + 1.
Example: 2's complement of $10110$ is $01001 + 1 = 01010$.

They represent negative numbers and turn subtraction into addition. Example $9 - 5$ in 4 bits:

```text
 1's complement method        2's complement method
   1001  (9)                    1001  (9)
 + 1010  (1's comp of 0101)   + 1011  (2's comp of 0101)
 ------                       ------
 1 0011                       1 0100
     +1  end-around carry      carry discarded
 ------                       
   0100  = 4                    0100  = 4
```

In 1's complement the end carry is added back; in 2's complement it is discarded. 2's complement has a single zero and is used in computers.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why can the BCD decoder outputs D8 and D9 be simplified to AD' and AD?
   A. Codes 1010-1111 never occur, so they are don't-cares
   B. A is always 1 in BCD
   C. B and C are always equal
   D. Inputs are inverted internally
   Answer: A. Since inputs 10-15 never occur, B and C need not be checked once A = 1. (Key point: Don't-care simplification)

2. How many outputs does a BCD (4-to-10) decoder have, and what does it activate?
   A. 16 outputs, two at a time
   B. 10 outputs, one for each decimal digit
   C. 4 outputs
   D. 7 outputs for the display
   Answer: B. A BCD-to-decimal decoder (IC 7442) activates one of ten lines for the digit 0-9. (Key point: Decoder size)

3. What is the 2's complement of 10110?
   A. 01001
   B. 01010
   C. 01011
   D. 10111
   Answer: B. The 1's complement is 01001; adding 1 gives 01010. (Key point: 2's complement example)

4. How is the end carry treated in 1's versus 2's complement subtraction?
   A. Both discard it
   B. 1's complement discards it; 2's adds it back
   C. 1's complement adds it back (end-around); 2's complement discards it
   D. Both add it back
   Answer: C. In 1's complement the end carry is added to the result; in 2's complement it is simply discarded. (Key point: End carry handling)

## Related in Digital Logic

- [Combinational vs sequential; BCD-to-decimal decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-to-decimal-decoder) — Digital Logic, chapter 4
- [BCD-to-seven-segment decoder, segments a and e](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-seven-segment-a-e) — Digital Logic, chapter 4
- [BCD-to-7-segment decoder; frequency counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abcd-7segment-frequency-counter) — Digital Logic, chapter 11
- [K-map Σ(0,1,4,8,10,11,12)+d, realize circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Akmap-realize-circuit-01248) — Digital Logic, chapter 3, asked 2×
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [DEMUX vs decoder; seven-segment "b" segment](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademux-decoder-b-segment) — Digital Logic, chapter 4

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