--- title: "4-bit bidirectional shift register" subject: "Digital Logic" chapter: 7 key: "semester_3/digital_logic:bidirectional-shift-register" source: https://www.bctengineer.com/q/semester_3/digital_logic/bidirectional-shift-register site: BCT Engineering --- # 4-bit bidirectional shift register Digital Logic · Chapter 7: Registers - Asked in: 2082 Baisakh, 6 marks - Video: [Bidirectional Shift Register](https://www.youtube.com/watch?v=zoEeQgQkPLA) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/bidirectional-shift-register - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-7 ## Question Explain operation of the 4-bit bidirectional shift register with truth table and timing diagram. ## Short answer A 4-bit bidirectional shift register uses a mode line R/L' to control direction. When R/L'=1 it shifts right (QA←DR, QB←QA, QC←QB, QD←QC); when R/L'=0 it shifts left (QD←DL, QC←QD, QB←QC, QA←QB). IC 74194 is a standard implementation. ## Answer A **bidirectional shift register** can shift its data either to the right or to the left, selected by a mode control line **RIGHT/LEFT'** (M). It uses four D flip-flops with a common clock and a 2-to-1 AND-OR selector in front of each D input. #### Circuit ```text One stage (stage B) of the register: QA ------------->+-----+ R/L' ---+------->| AND |--+ | +-----+ | +----+ | +->| OR |--> DB | +-----+ +->| | +-[NOT]->| AND |--+ +----+ QC ------------->+-----+ DB = M.QA + M'.QC (M = R/L') Full register: DR ->[sel]->FF-A <-> [sel]->FF-B <-> [sel]->FF-C <-> [sel]->FF-D <-[sel]<- DL DA = M.DR + M'.QB DB = M.QA + M'.QC DC = M.QB + M'.QD DD = M.QC + M'.DL ``` - **M = 1 (shift right):** the upper AND gates are enabled. Each flip-flop takes the output of the stage on its **left**: $QA \leftarrow DR,\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$. Serial data enters at DR and leaves at QD. - **M = 0 (shift left):** the lower AND gates are enabled. Each flip-flop takes the output of the stage on its **right**: $QD \leftarrow DL,\ QC \leftarrow QD,\ QB \leftarrow QC,\ QA \leftarrow QB$. Serial data enters at DL and leaves at QA. #### Truth (function) table | R/L' (M) | CLK | QA+ | QB+ | QC+ | QD+ | Operation | |---|---|---|---|---|---|---| | x | no edge | QA | QB | QC | QD | Hold | | 1 | rising edge | DR | QA | QB | QC | Shift right | | 0 | rising edge | QB | QC | QD | DL | Shift left | #### Example and timing diagram Starting from 0000: shift right for 4 clocks with DR = 1, 0, 1, 1; then shift left for 3 clocks with DL = 0, 1, 1. | CLK | Mode | DR | DL | QA | QB | QC | QD | |---|---|---|---|---|---|---|---| | 0 | - | - | - | 0 | 0 | 0 | 0 | | 1 | Right | 1 | x | 1 | 0 | 0 | 0 | | 2 | Right | 0 | x | 0 | 1 | 0 | 0 | | 3 | Right | 1 | x | 1 | 0 | 1 | 0 | | 4 | Right | 1 | x | 1 | 1 | 0 | 1 | | 5 | Left | x | 0 | 1 | 0 | 1 | 0 | | 6 | Left | x | 1 | 0 | 1 | 0 | 1 | | 7 | Left | x | 1 | 1 | 0 | 1 | 1 | ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| R/L' ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|____________ DR ‾‾‾|___|‾‾‾‾‾‾‾|____________ DL ___________________|‾‾‾‾‾‾‾| QA _|‾‾‾|___|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾ QB _____|‾‾‾|___|‾‾‾|___|‾‾‾|__ QC _________|‾‾‾|___|‾‾‾|___|‾‾ QD _____________|‾‾‾|___|‾‾‾‾‾‾ ``` During clocks 1 to 4 the bits move towards QD; from clock 5 the direction reverses and the bits move towards QA while new bits enter at QD. Bidirectional (universal) shift registers such as IC 74194 are used for multiplication/division by 2 and in serial data handling. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does M (RIGHT/LEFT') = 1 do? A. Shifts left: QA gets QB B. Holds the data C. Shifts right: QA gets DR, QB gets QA, and so on D. Loads in parallel Answer: C. M = 1 enables the upper AND gates. (Key point: Shift right) 2. In shift-left mode, where does serial data enter and leave? A. Enters at DR and leaves at QD B. Enters at QA and leaves at DL C. Enters at DL and leaves at QD D. Enters at DL and leaves at QA Answer: D. Data moves towards QA, so QD takes DL and QA is the output. (Key point: Shift left) 3. What is the D input of stage B? A. DB = M.QA + M'.QC B. DB = M.QC + M'.QA C. DB = QA.QC D. DB = M + QA Answer: A. M = 1 selects QA (right), M = 0 selects QC (left). (Key point: Stage logic) 4. After 4 right shifts of 1,0,1,1 then one left shift with DL = 0, what is QA QB QC QD? A. 1011 B. 1010 C. 0101 D. 0110 Answer: B. After clock 4 it is 1101; shifting left with 0 entering gives 1010. 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