--- title: "3-bit multiplier with binary parallel adder" subject: "Digital Logic" chapter: 5 key: "semester_3/digital_logic:binary-multiplier-3bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/binary-multiplier-3bit site: BCT Engineering --- # 3-bit multiplier with binary parallel adder Digital Logic · Chapter 5: Arithmetic Circuits - Asked in: 2078 Bhadra, 6 marks - Video: [Binary Multiplier in Digital Logic Design | 2 bit, 3 bit Multiplier Explained](https://www.youtube.com/watch?v=k80qC-B7AAw) — EE-Vibes (Electrical Engineering Lessons) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/binary-multiplier-3bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5 ## Question Design a 3 bit binary multiplier using binary parallel adder (BPA). ## Short answer Multiply A2A1A0 by B2B1B0 using 9 AND gates for partial products. Sum the three rows with two 3-bit parallel adders: P0 = A0B0; first adder adds the second row to shifted first row, producing P1; second adder adds the third row to the remaining sums, yielding P2–P5. ## Answer A **3-bit binary multiplier** multiplies $A = A_2A_1A_0$ by $B = B_2B_1B_0$ to give a 6-bit product $P_5\dots P_0$. Partial products are made with AND gates and added with binary parallel adders (BPA). #### Partial products ```text A2 A1 A0 x B2 B1 B0 ----------------------------- A2B0 A1B0 A0B0 A2B1 A1B1 A0B1 A2B2 A1B2 A0B2 ----------------------------- P5 P4 P3 P2 P1 P0 ``` - $3 \times 3 = 9$ AND gates make the partial-product bits. - Two 3-bit parallel adders add the three rows. #### Design steps 1. $P_0 = A_0B_0$ directly. 2. **Adder 1 (3-bit):** adds row 1 ($A_2B_1, A_1B_1, A_0B_1$) to ($0, A_2B_0, A_1B_0$). LSB of its sum gives $P_1$. 3. **Adder 2 (3-bit):** adds row 2 ($A_2B_2, A_1B_2, A_0B_2$) to (carry of adder 1, upper two sum bits of adder 1). LSB gives $P_2$, the next two sum bits give $P_3P_4$, and its carry is $P_5$. ```text A2B0 A1B0 A0B0 -----------------------> P0 | | 0 A2B0 A1B0 + A2B1 A1B1 A0B1 [ 3-bit BPA #1 ] --- S0 --------> P1 C, S2, S1 + A2B2 A1B2 A0B2 [ 3-bit BPA #2 ] --- S0 --------> P2 C S2 S1 | | +--------------------> P3 | +-------------------------> P4 +------------------------------> P5 ``` Both adders have carry-in $= 0$. #### Example: $101 \times 011$ (5 × 3) | Step | Operation | Result | Product bit | |---|---|---|---| | Row 0 | $A\cdot B_0 = 101$ | pass 010 | $P_0 = 1$ | | Adder 1 | $010 + 101$ ($A\cdot B_1$) | 0 111 | $P_1 = 1$, pass 011 | | Adder 2 | $011 + 000$ ($A\cdot B_2$) | 0 011 | $P_2 = 1$, $P_5P_4P_3 = 001$ | **Product** $= 001111_2 = 15$, and $5 \times 3 = 15$. **Hardware needed:** 9 AND gates and two 3-bit parallel adders (or two 4-bit adders such as IC 7483 with the top bit tied to 0). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many AND gates for a 3x3 multiplier? A. 9 B. 6 C. 3 D. 12 Answer: A. 3 x 3 partial product bits. (Key point: AND gates) 2. How many 3-bit parallel adders are used? A. 1 B. 2 C. 3 D. 4 Answer: B. Three rows need two additions. (Key point: Adders) 3. How many bits does the product have? A. 3 B. 5 C. 6 D. 9 Answer: C. 3 + 3 = 6 bits, P5 to P0. (Key point: Product bits) 4. 5 x 3 gives A. 001110 = 14 B. 010101 = 21 C. 000111 = 7 D. 001111 = 15 Answer: D. 101 x 011 = 15. (Key point: Example) ## Related in Digital Logic - [4-bit multiplier with parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-4bit) — Digital Logic, chapter 5 - [Short note: binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashort-note-binary-parallel-adder) — Digital Logic, chapter 5 - [Two 4-bit parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparallel-adder-4bit) — Digital Logic, chapter 5 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 - [4-bit ripple carry adder and its problems](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aripple-carry-adder-problems) — Digital Logic, chapter 5 ## Related in other subjects - [Two-tape TM as binary adder](https://www.bctengineer.com/question.md?key=semester_3%2Ftheory_of_computation%3Atm-two-tape-binary-adder) — Theory of Computation, chapter 4 - [Bit error probability for binary ASK](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Abinary-ask-ber) — Communication Systems, chapter 9