--- title: "4-bit multiplier with parallel adder" subject: "Digital Logic" chapter: 5 key: "semester_3/digital_logic:binary-multiplier-4bit" source: https://www.bctengineer.com/q/semester_3/digital_logic/binary-multiplier-4bit site: BCT Engineering --- # 4-bit multiplier with parallel adder Digital Logic · Chapter 5: Arithmetic Circuits - Asked in: 2069 Chaitra, 8 marks - Video: [[51] 4 bit by 3 bit binary multiplier logic circuit design](https://www.youtube.com/watch?v=pJJVj1hNOjY) — Mostafa Abdelrehim, PhD - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/binary-multiplier-4bit - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-5 ## Question Design a combinational logic that performs multiplication between two 4 bit numbers using binary parallel adder and other gates. ## Short answer 16 AND gates form partial products A_jB_i. Three 4-bit parallel adders sum the rows: LSB of first row is P0; adder1 adds row1 to upper bits, LSB is P1; adder2 adds row2, LSB is P2; adder3 adds row3, outputs P7-P4 and LSB is P3. Example: 1101×1011 = 10001111 (143). ## Answer A **binary multiplier** multiplies two numbers by forming partial products with AND gates and adding them with binary parallel adders (BPA), in the same way as long multiplication by hand. Let $A = A_3A_2A_1A_0$ (multiplicand) and $B = B_3B_2B_1B_0$ (multiplier). The product has $4 + 4 = 8$ bits, $P_7 \dots P_0$. #### Partial products ```text A3 A2 A1 A0 x B3 B2 B1 B0 ------------------------------------ A3B0 A2B0 A1B0 A0B0 A3B1 A2B1 A1B1 A0B1 A3B2 A2B2 A1B2 A0B2 A3B3 A2B3 A1B3 A0B3 ------------------------------------ P7 P6 P5 P4 P3 P2 P1 P0 ``` Each partial-product bit $A_jB_i$ is one 2-input AND gate, so **16 AND gates** are needed. Adding the four rows needs **three 4-bit parallel adders**. #### Design 1. **Row 0:** $A_3B_0\,A_2B_0\,A_1B_0\,A_0B_0$. Its LSB $A_0B_0$ is directly $P_0$. 2. **Adder 1:** adds row 1 ($A_3B_1 \dots A_0B_1$) to the upper three bits of row 0 ($0, A_3B_0, A_2B_0, A_1B_0$). Its sum LSB is $P_1$; its carry and upper three sum bits go on. 3. **Adder 2:** adds row 2 ($A_3B_2 \dots A_0B_2$) to (carry of adder 1, upper three sum bits of adder 1). Its sum LSB is $P_2$. 4. **Adder 3:** adds row 3 ($A_3B_3 \dots A_0B_3$) to (carry of adder 2, upper three sum bits of adder 2). Its four sum bits give $P_6P_5P_4P_3$ and its carry gives $P_7$. ```text A x B0 (4 AND) -> [b3 b2 b1 | b0=P0] | A x B1 (4 AND) -> [ 4-bit BPA #1 ] -> s0 = P1 | carry + s3 s2 s1 A x B2 (4 AND) -> [ 4-bit BPA #2 ] -> s0 = P2 | carry + s3 s2 s1 A x B3 (4 AND) -> [ 4-bit BPA #3 ] -> s0 = P3 | Cout=P7, s3 s2 s1 = P6 P5 P4 ``` Each adder's carry-in $C_0 = 0$. #### Example: $1101 \times 1011$ (13 × 11) | Step | Operation | Result | Product bit | |---|---|---|---| | Row 0 | $A \cdot B_0 = 1101$ | upper bits 0110 | $P_0 = 1$ | | Adder 1 | $0110 + 1101$ ($A\cdot B_1$) | 1 0011 | $P_1 = 1$, pass 1001 | | Adder 2 | $1001 + 0000$ ($A\cdot B_2$) | 0 1001 | $P_2 = 1$, pass 0100 | | Adder 3 | $0100 + 1101$ ($A\cdot B_3$) | 1 0001 | $P_3 = 1$, $P_7P_6P_5P_4 = 1000$ | **Product** $= 1000\,1111_2 = 143$, and $13 \times 11 = 143$. **Hardware:** 16 AND gates and three 4-bit parallel adders (e.g. three IC 7483). In general an $n \times m$-bit multiplier needs $n \cdot m$ AND gates and $(m-1)$ $n$-bit adders. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many 2-input AND gates form the partial products of a 4x4 multiplier? A. 16 B. 8 C. 12 D. 4 Answer: A. Each of the 4x4 bit pairs needs one AND gate. (Key point: AND gates) 2. How many 4-bit parallel adders add the four partial-product rows? A. 4 B. 3 C. 2 D. 1 Answer: B. Four rows need three additions. (Key point: Adders) 3. How many bits does the product of two 4-bit numbers have? A. 4 B. 5 C. 8 D. 16 Answer: C. Up to 4 + 4 = 8 bits. (Key point: Product width) 4. How is P0 obtained? A. From adder 1 carry B. From adder 3 sum C. As A3B3 D. Directly from A0B0 Answer: D. The LSB of the first row is not added to anything. (Key point: Product bit P0) ## Related in Digital Logic - [3-bit multiplier with binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Abinary-multiplier-3bit) — Digital Logic, chapter 5 - [Two 4-bit parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aparallel-adder-4bit) — Digital Logic, chapter 5 - [Short note: binary parallel adder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ashort-note-binary-parallel-adder) — Digital Logic, chapter 5 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 - [Define combinational logic circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acombinational-circuit-define) — Digital Logic, chapter 3 - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 ## Related in other subjects - [Two-tape TM as binary adder](https://www.bctengineer.com/question.md?key=semester_3%2Ftheory_of_computation%3Atm-two-tape-binary-adder) — Theory of Computation, chapter 4 - [C program: sum of two 8-bit BCD numbers](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-bcd-sum-c) — Embedded System, chapter 9 - [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3