--- title: "CMOS characteristics; 2-input CMOS NOR" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:cmos-characteristics-nor-2input" source: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-characteristics-nor-2input site: BCT Engineering --- # CMOS characteristics; 2-input CMOS NOR Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2081 Baisakh, 3+5 marks - Video: [CMOS NOR Gate Explained: Circuit, Working, Implementation, and Truth Table](https://www.youtube.com/watch?v=E4KPiq3GlSs) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-characteristics-nor-2input - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Explain the characteristics of CMOS gates and explain logic operation of CMOS 2-input NOR gate circuit with its truth table. ## Short answer CMOS gates feature near-zero static power, wide supply range (3-15V for 4000B), high noise margin (~30% VDD), and rail-to-rail output. A 2-input CMOS NOR uses series PMOS and parallel NMOS; output is high only when both inputs are low, otherwise low. ## Answer #### Characteristics of CMOS gates CMOS (complementary MOS) gates use PMOS pull-up and NMOS pull-down transistors in pairs. Main characteristics (4000B and 74HC series): | Characteristic | Typical value / remark | |---|---| | Supply voltage | 3–15 V (4000B), 2–6 V (74HC) | | Logic levels (5 V CMOS, typical) | $V_{IL} \le 1.5$ V, $V_{IH} \ge 3.5$ V, $V_{OL} \approx 0.1$ V, $V_{OH} \approx 4.9$ V | | Static power | almost zero (nW per gate) | | Dynamic power | $P_D = C_L V_{DD}^2 f$, rises with frequency | | Noise margin | high, about 30% of $V_{DD}$ (1.4 V at 5 V) | | Propagation delay | 25–100 ns (4000B), about 8–10 ns (74HC) | | Fan-out | very high (about 50) because MOS inputs draw almost no current | | Handling | gate oxide is damaged by static charge; unused inputs must be tied to $V_{DD}$ or ground | #### 2-input CMOS NOR gate Two PMOS transistors $P_1$, $P_2$ are in **series** from $V_{DD}$ to the output, and two NMOS transistors $N_1$, $N_2$ are in **parallel** from the output to ground. Input A drives $P_1$ and $N_1$; input B drives $P_2$ and $N_2$. ```text VDD | A --o| P1 | B --o| P2 | +---------- Y = (A+B)' | | A ---| N1 B ---| N2 | | GND GND ``` A PMOS is ON when its gate is 0; an NMOS is ON when its gate is 1. **Operation:** - **A = 0, B = 0:** $P_1$, $P_2$ ON; $N_1$, $N_2$ OFF. Output connected to $V_{DD}$ → **Y = 1**. - **A = 0, B = 1:** $N_2$ ON pulls output to ground; $P_2$ OFF breaks the pull-up path → **Y = 0**. - **A = 1, B = 0:** $N_1$ ON, $P_1$ OFF → **Y = 0**. - **A = 1, B = 1:** both NMOS ON, both PMOS OFF → **Y = 0**. | A | B | P1 | P2 | N1 | N2 | Y | |---|---|---|---|---|---|---| | 0 | 0 | ON | ON | OFF | OFF | 1 | | 0 | 1 | ON | OFF | OFF | ON | 0 | | 1 | 0 | OFF | ON | ON | OFF | 0 | | 1 | 1 | OFF | OFF | ON | ON | 0 | So $Y = \overline{A + B}$. Since the pull-up and pull-down networks are never ON together in steady state, no DC path exists from $V_{DD}$ to ground, which is why CMOS static power is so low. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How does CMOS power dissipation behave? A. Static power is high and dynamic power is zero B. Both are independent of frequency C. Static power is almost zero, while dynamic power C_L V_DD^2 f rises with frequency D. Dynamic power is independent of supply voltage Answer: C. CMOS draws current mainly when switching, so power grows with f and with V_DD^2. (Key point: Static vs dynamic power) 2. Why is CMOS fan-out very high (about 50)? A. MOS inputs draw almost no DC current B. Outputs can supply very large currents C. Supply voltage is 15 V D. Propagation delay is very short Answer: A. The gate oxide isolates the input, so loading is limited by capacitance, not current. (Key point: Fan-out) 3. In a 2-input CMOS NOR gate, how are the transistors connected? A. PMOS in parallel, NMOS in series B. All four in series C. PMOS in series, NMOS in series D. PMOS in series, NMOS in parallel Answer: D. Series PMOS gives Y=1 only when both inputs are 0; parallel NMOS pulls Y low if either input is 1. (Key point: 2-input NOR structure) 4. For A = 0 and B = 1 in the CMOS NOR gate, which is correct? A. P1 and P2 are both ON, so Y = 1 B. N2 is ON and P2 is OFF, so Y = 0 C. N1 is ON and P1 is OFF, so Y = 0 D. Both NMOS are OFF, so Y floats Answer: B. B = 1 turns ON N2 and turns OFF P2, breaking the pull-up path and grounding Y. (Key point: NOR operation) 5. What precaution is needed for CMOS gates? A. Protect against static charge and never leave unused inputs floating B. Always connect unused inputs to the output C. Operate only at exactly 5 V D. Use a totem-pole output for each input Answer: A. Gate oxide is damaged by static, and floating inputs cause unpredictable behaviour; tie unused inputs to VDD or ground. (Key point: Handling) ## Related in Digital Logic - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10 - [3-input CMOS gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-three-input-gate) — Digital Logic, chapter 10 - [3-input XNOR using NOR gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xnor-nor) — Digital Logic, chapter 2 - [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2 - [TTL NOR gate; 74XX characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-74xx-characteristics) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2× - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6