--- title: "CMOS inverter operation" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:cmos-inverter" source: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-inverter site: BCT Engineering --- # CMOS inverter operation Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2078 Kartik, 4 marks - Video: [CMOS Inverter (Meaning, Circuit & Working) Explained | VLSI by Engineering Funda](https://www.youtube.com/watch?v=kvR_UabB108) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-inverter - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Explain the operation of a CMOS inverter with a circuit diagram. ## Short answer A CMOS inverter consists of a PMOS pull-up and NMOS pull-down with gates tied as input and drains as output. When input is low, the PMOS is on and NMOS off, pulling output to VDD; when input is high, the NMOS is on and PMOS off, giving 0 V. In either steady state one transistor is off, so static power is nearly zero. ## Answer A **CMOS inverter** is the basic CMOS gate: one PMOS and one NMOS enhancement MOSFET in series between $V_{DD}$ and ground, with their gates joined as the input and their drains joined as the output. ```text VDD | s +---o| Q1 (PMOS) | d A-+ +-------- Y = A' | d +----| Q2 (NMOS) s | GND ``` #### Operation - **A = 0 (0 V):** for the PMOS, $V_{GS} = -V_{DD}$, so Q1 is **ON**; for the NMOS, $V_{GS} = 0$, so Q2 is **OFF**. The output is connected to $V_{DD}$ through Q1's low ON resistance → **Y = 1**. - **A = 1 ($V_{DD}$):** Q1 has $V_{GS} = 0$ → **OFF**; Q2 has $V_{GS} = V_{DD}$ → **ON**. The output is connected to ground → **Y = 0**. | A | Q1 (PMOS) | Q2 (NMOS) | Y | |---|---|---|---| | 0 | ON | OFF | 1 | | 1 | OFF | ON | 0 | #### Features - In either steady state one transistor is OFF, so **no DC current** flows from $V_{DD}$ to ground: static power is almost zero. Current flows only briefly while switching and to charge the load capacitance ($P_D = C_L V_{DD}^2 f$). - Output swings nearly from 0 to $V_{DD}$; the switching threshold is about $V_{DD}/2$, giving a high noise margin. - Very high input resistance gives a large fan-out. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is a CMOS inverter connected? A. PMOS and NMOS in series between VDD and ground, gates joined as input, drains joined as output B. Two NMOS in parallel with a resistor C. PMOS and NMOS in parallel between VDD and output D. PMOS and NMOS with separate gate inputs Answer: A. Joined gates form A; joined drains form Y. (Key point: Structure) 2. When A = 0, what happens? A. PMOS is OFF, NMOS is ON, so Y = 1 B. PMOS is ON (V_GS = -VDD), NMOS is OFF, so Y = 1 C. Both are ON, so Y is half VDD D. PMOS is ON, NMOS is ON, so Y = 0 Answer: B. The PMOS connects the output to VDD while the NMOS is off. (Key point: Input LOW) 3. When A = VDD, why is Y = 0? A. PMOS turns ON and connects Y to ground B. NMOS is OFF and Y floats low C. NMOS has V_GS = VDD and turns ON, connecting Y to ground; PMOS has V_GS = 0 and is OFF D. Both transistors are OFF Answer: C. The NMOS pulls Y to ground. (Key point: Input HIGH) 4. Why is static power nearly zero? A. The supply voltage is low B. Both transistors are ON but have high resistance C. The input draws no capacitance D. One transistor is always OFF in steady state, so no DC path from VDD to ground Answer: D. Current flows only briefly while switching and charging the load capacitance. (Key point: Static power) 5. What is the CMOS dynamic power expression? A. P_D = V_DD I_CC B. P_D = C_L V_DD^2 f C. P_D = V_DD / f D. P_D = C_L f / V_DD Answer: B. Power grows with load capacitance, frequency and the square of supply voltage. (Key point: Dynamic power) ## Related in Digital Logic - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10 - [3-input CMOS gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-three-input-gate) — Digital Logic, chapter 10 - [Frequency counter operation with block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afrequency-counter) — Digital Logic, chapter 11, asked 14× - [CMOS characteristics; 2-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-nor-2input) — Digital Logic, chapter 10 - [CMOS parameters; 2-input CMOS NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-parameters-nand-2input) — Digital Logic, chapter 10 - [TTL voltage profile; TTL-to-CMOS interface](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-voltage-profile-ttl-cmos-interface) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [CMOS switch operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-switch) — Basic Electronics Engineering, chapter 3 - [Wien bridge oscillator circuit and operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Awien-bridge-draw-explain) — Basic Electronics Engineering, chapter 4, asked 4× - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2