--- title: "CMOS parameters; 2-input CMOS NAND" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:cmos-parameters-nand-2input" source: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-parameters-nand-2input site: BCT Engineering --- # CMOS parameters; 2-input CMOS NAND Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2079 Baisakh, 3+5 marks - Video: [CMOS NAND Gate Explained: Circuit, Working, Implementation, and Truth Table](https://www.youtube.com/watch?v=YAQbPbI-2XI) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-parameters-nand-2input - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Define CMOS parameters shortly and explain logic operation of CMOS 2-input NAND gate circuit with its truth table. ## Short answer CMOS parameters: VDD 3-15V (4000B) or 2-6V (74HC), VIH(min)=3.5V, VIL(max)=1.5V, noise margin 1.4V, static power ~0, dynamic power CV^2f, delay 8-10ns (74HC). A 2-input CMOS NAND has parallel PMOS and series NMOS; output is low only when both inputs are high. ## Answer #### CMOS parameters The main parameters of a CMOS gate (typical 5 V values): - **Supply voltage $V_{DD}$:** 3–15 V (4000B), 2–6 V (74HC). - **Input levels:** $V_{IH(min)} \approx 3.5$ V (70% of $V_{DD}$), $V_{IL(max)} \approx 1.5$ V (30% of $V_{DD}$). - **Output levels:** $V_{OH(min)} \approx 4.9$ V, $V_{OL(max)} \approx 0.1$ V (almost rail to rail). - **Noise margin:** $NM_H = 4.9 - 3.5 = 1.4$ V, $NM_L = 1.5 - 0.1 = 1.4$ V. - **Power dissipation:** nearly zero when static; dynamic $P_D = C_L V_{DD}^2 f$. - **Propagation delay:** about 8–10 ns (74HC), 25–100 ns (4000B). - **Fan-out:** about 50, limited by input capacitance, not by current. #### 2-input CMOS NAND gate ```text VDD VDD | | A --o| P1 B --o| P2 | | +--------+--------+ | +------------ Y = (AB)' | A --| N1 | B --| N2 | GND ``` (P = PMOS, ON when gate = 0; N = NMOS, ON when gate = 1.) The two PMOS transistors are in **parallel** between $V_{DD}$ and the output; the two NMOS transistors are in **series** between the output and ground. - **A = 0 or B = 0:** at least one PMOS is ON, connecting Y to $V_{DD}$, and the series NMOS path is broken → **Y = 1**. - **A = 1 and B = 1:** both NMOS are ON, connecting Y to ground; both PMOS are OFF → **Y = 0**. | A | B | P1 | P2 | N1 | N2 | Y | |---|---|---|---|---|---|---| | 0 | 0 | ON | ON | OFF | OFF | 1 | | 0 | 1 | ON | OFF | OFF | ON | 1 | | 1 | 0 | OFF | ON | ON | OFF | 1 | | 1 | 1 | OFF | OFF | ON | ON | 0 | So $Y = \overline{AB}$. In no input state are both networks ON, so no DC current flows from $V_{DD}$ to ground. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What are typical CMOS input levels at VDD = 5 V? A. VIH(min) = 2.0 V and VIL(max) = 0.8 V B. VIH(min) about 3.5 V and VIL(max) about 1.5 V C. VIH(min) = 4.9 V and VIL(max) = 0.1 V D. VIH(min) = 2.4 V and VIL(max) = 0.4 V Answer: B. They are 70% and 30% of VDD. (Key point: CMOS input levels) 2. How is NM_H computed for CMOS at 5 V? A. VOH(min) - VIH(min) = 4.9 - 3.5 = 1.4 V B. VIH(min) - VIL(max) = 2.0 V C. VOH(min) - VOL(max) = 4.8 V D. VIL(max) - VOL(max) = 1.4 V Answer: A. NM_H is the output HIGH minimum minus the input HIGH minimum. (Key point: Noise margin calculation) 3. How are the transistors arranged in a 2-input CMOS NAND? A. PMOS in series, NMOS in parallel B. Both pairs in parallel C. PMOS in parallel, NMOS in series D. Both pairs in series Answer: C. Either input LOW turns ON a parallel PMOS; Y goes LOW only when both series NMOS are ON. (Key point: NAND structure) 4. For A = 0 and B = 1 in the CMOS NAND, what is the result? A. Both NMOS conduct so Y = 0 B. Both PMOS are OFF so Y = 1 C. No path exists so Y floats D. P1 is ON and N1 is OFF, so Y = 1 Answer: D. A = 0 turns ON P1 (connecting Y to VDD) and turns OFF N1 (breaking the series path). (Key point: NAND operation) 5. What limits CMOS fan-out of about 50? A. Input current B. Input capacitance, not current C. Supply voltage D. Noise margin Answer: B. MOS inputs draw almost no DC current; capacitive loading slows the gate. (Key point: Fan-out limit) ## Related in Digital Logic - [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10 - [3-input CMOS gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-three-input-gate) — Digital Logic, chapter 10 - [CMOS NAND gate; totem-pole output](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-nand-totem-pole) — Digital Logic, chapter 10 - [CMOS characteristics; 2-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-nor-2input) — Digital Logic, chapter 10 - [2-input TTL NAND gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-2input) — Digital Logic, chapter 10 - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [CMOS NAND, NOR (and NOT) circuits](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acmos-nand-nor-circuits) — Embedded System, chapter 8, asked 2× - [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6 - [Encoder; NAND and XOR truth tables](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aencoder-truth-tables) — Basic Electronics Engineering, chapter 6