--- title: "3-input CMOS gate" subject: "Digital Logic" chapter: 10 key: "semester_3/digital_logic:cmos-three-input-gate" source: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-three-input-gate site: BCT Engineering --- # 3-input CMOS gate Digital Logic · Chapter 10: Digital Integrated Circuits - Asked in: 2075 Chaitra, 6 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/cmos-three-input-gate - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-10 ## Question Draw the circuit diagram of 3 input CMOS gate and explain its operation. ## Short answer In a 3-input CMOS NAND gate, three PMOS transistors are in parallel between VDD and output, and three NMOS are in series from output to ground. If any input is 0, at least one PMOS turns on, pulling output high; only when all inputs are 1 do all NMOS turn on, pulling output low, so Y = (ABC)'. ## Answer A 3-input CMOS gate uses three PMOS–NMOS pairs. The **3-input CMOS NAND** gate is shown: three PMOS in **parallel** from $V_{DD}$ to the output and three NMOS in **series** from the output to ground; each input drives one PMOS and one NMOS. ```text VDD VDD VDD | | | A --o| P1 B --o| P2 C --o| P3 | | | +------------+------------+ | +-------------- Y = (ABC)' | A --| N1 | B --| N2 | C --| N3 | GND ``` #### Operation - A PMOS conducts when its gate is 0; an NMOS conducts when its gate is 1. - **Any input 0:** the PMOS of that input is ON and connects Y to $V_{DD}$; the NMOS of that input is OFF, breaking the series path to ground → **Y = 1**. - **All inputs 1:** all PMOS are OFF; all three series NMOS are ON and connect Y to ground → **Y = 0**. | A | B | C | PMOS ON | NMOS chain | Y | |---|---|---|---|---|---| | 0 | 0 | 0 | P1 P2 P3 | open | 1 | | 0 | 0 | 1 | P1 P2 | open | 1 | | 0 | 1 | 0 | P1 P3 | open | 1 | | 0 | 1 | 1 | P1 | open | 1 | | 1 | 0 | 0 | P2 P3 | open | 1 | | 1 | 0 | 1 | P2 | open | 1 | | 1 | 1 | 0 | P3 | open | 1 | | 1 | 1 | 1 | none | closed | 0 | So $Y = \overline{ABC}$. The pull-up and pull-down networks are never ON together, so static power is almost zero. **3-input NOR:** swapping the arrangement (PMOS in series, NMOS in parallel) gives $Y = \overline{A + B + C}$: Y = 1 only when all inputs are 0. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the 3-input CMOS NAND arranged? A. 3 PMOS in parallel and 3 NMOS in series B. 3 PMOS in series and 3 NMOS in parallel C. All six in series D. All PMOS and NMOS in parallel Answer: A. Parallel PMOS pull up if any input is 0; series NMOS pull down only if all are 1. (Key point: NAND structure) 2. Why is Y = 1 when any input is 0? A. That input's NMOS grounds Y B. That input's PMOS connects Y to VDD and its NMOS breaks the series path to ground C. All PMOS turn OFF D. The output floats Answer: B. A PMOS conducts with gate 0 and an NMOS needs gate 1. (Key point: Any input 0) 3. When A = B = C = 1, what is Y? A. 1, because all PMOS are ON B. 0, because only one NMOS is ON C. 0, because all three series NMOS are ON and all PMOS OFF D. Hi-Z, because both networks are OFF Answer: C. The closed NMOS chain grounds Y. (Key point: All inputs 1) 4. Why is static power almost zero? A. The gate uses very low current resistors B. Inputs are connected to ground C. The supply is below 1 V D. Pull-up and pull-down networks are never ON together Answer: D. No DC path exists between VDD and ground. (Key point: Static power) 5. How does the 3-input CMOS NOR differ? A. PMOS in series and NMOS in parallel; Y = 1 only when all inputs are 0 B. PMOS in parallel and NMOS in series; Y = 1 only when all inputs are 1 C. Same as NAND but with inverted output D. PMOS in series and NMOS in series Answer: A. Swapping the arrangement gives Y = (A+B+C)'. (Key point: NOR variant) ## Related in Digital Logic - [Propagation delay; 3-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apropagation-delay-cmos-nor-3input) — Digital Logic, chapter 10 - [CMOS characteristics; 2-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-nor-2input) — Digital Logic, chapter 10 - [CMOS parameters; 2-input CMOS NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-parameters-nand-2input) — Digital Logic, chapter 10 - [CMOS characteristics; TTL 2-input AND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-ttl-and) — Digital Logic, chapter 10 - [2-input TTL NAND; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nand-cmos-characteristics) — Digital Logic, chapter 10 - [TTL NOR gate; CMOS characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-nor-cmos-characteristics) — Digital Logic, chapter 10 ## Related in other subjects - [CMOS inverter / NOT gate operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-inverter-operation) — Basic Electronics Engineering, chapter 3, asked 4× - [CMOS switch operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acmos-switch) — Basic Electronics Engineering, chapter 3 - [Thyristor gate triggering circuit](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_electronics%3Athyristor-gate-triggering-circuit) — Power Electronics, chapter 1 - [Thyristor V-I, latching/holding, gate signal circuit](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_electronics%3Athyristor-vi-latching-gate-circuit) — Power Electronics, chapter 1