--- title: "Counter; MOD-6 synchronous counter" subject: "Digital Logic" chapter: 8 key: "semester_3/digital_logic:counter-mod6-synchronous" source: https://www.bctengineer.com/q/semester_3/digital_logic/counter-mod6-synchronous site: BCT Engineering --- # Counter; MOD-6 synchronous counter Digital Logic · Chapter 8: Counters - Asked in: 2068 Baisakh - Video: [MOD 6 Synchronous Counter Using D Flip flop | MOD 6 Counter](https://www.youtube.com/watch?v=NlLoLONTqHQ) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/counter-mod6-synchronous - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-8 ## Question What is a counter? Design a MOD-6 synchronous counter. Draw its timing diagram. ## Short answer A counter is a sequential circuit with a fixed state sequence. A MOD-6 synchronous counter uses three T flip-flops. T0=1, T1=Q2'Q0, T2=Q2Q0+Q1Q0. It counts 0-5, with states 6,7 don't cares. The timing diagram shows Q0 toggling each clock, Q2 dividing frequency by 6. ## Answer #### Counter A **counter** is a sequential circuit made of flip-flops that goes through a fixed sequence of states when clock pulses are applied. The number of distinct states is its **modulus** (MOD-N). Counters are used to count pulses, divide frequency and generate timing signals. They are synchronous (common clock) or asynchronous (ripple). #### Design of MOD-6 synchronous counter (T flip-flops) **Step 1:** Sequence 000 → 001 → 010 → 011 → 100 → 101 → 000. $2^3 = 8 \ge 6$, so 3 T flip-flops with a common clock. States 110 and 111 are don't cares. For a T flip-flop, $T = Q \oplus Q^+$. **Step 2: Excitation table** | Present Q2Q1Q0 | Next Q2Q1Q0 | T2 | T1 | T0 | |---|---|---|---|---| | 000 | 001 | 0 | 0 | 1 | | 001 | 010 | 0 | 1 | 1 | | 010 | 011 | 0 | 0 | 1 | | 011 | 100 | 1 | 1 | 1 | | 100 | 101 | 0 | 0 | 1 | | 101 | 000 | 1 | 0 | 1 | **Step 3: K-maps** | T1: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | X | X | | T2: Q2 / Q1Q0 | 00 | 01 | 11 | 10 | |---|---|---|---|---| | 0 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | X | X | $T_0 = 1$ in every row. **Step 4: Equations** $$ \begin{aligned} &T_2 = Q_2Q_0 + Q_1Q_0 \\ &T_1 = \overline{Q_2}Q_0 \\ &T_0 = 1 \end{aligned} $$ **Step 5: Circuit diagram** ```text +-----+ +-----+ +-----+ T0>|T Q|-Q0 T1>|T Q|-Q1 T2>|T Q|-Q2 | FF0 | | FF1 | | FF2 | | | | | | | +--o--+ +--o--+ +--o--+ | | | CLK---+-------------+-------------+ T0 = 1 T1 = Q2'.Q0 T2 = Q2.Q0 + Q1.Q0 ``` Unused states: 110 → 111 → 010, so the counter is self-starting. **Step 6: Timing diagram** ```text CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾ Q2 ________________|‾‾‾‾‾‾‾|_______ Q1 ________|‾‾‾‾‾‾‾|_______________ Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾ Cnt 0 1 2 3 4 5 0 1 ``` All flip-flops change together on the falling clock edge. $Q_2$ is high for counts 4 and 5, so it divides the clock by 6. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. A counter that cycles through 6 distinct states has which modulus, and how many flip-flops are needed at minimum? A. MOD-6, 2 flip-flops B. MOD-6, 3 flip-flops C. MOD-8, 3 flip-flops D. MOD-3, 6 flip-flops Answer: B. The number of distinct states is the modulus (6). Since 2^3 = 8 >= 6 and 2^2 = 4 < 6, 3 flip-flops are required. (Key point: Counter modulus) 2. For a T flip-flop, how is the required T input found from present state Q and next state Q+? A. T = Q AND Q+ B. T = Q XOR Q+ C. T = Q+ D. T = NOT Q+ Answer: B. T must be 1 only when the flip-flop has to change state, so T = Q XOR Q+. (Key point: T excitation) 3. Which set of equations is the result of the MOD-6 synchronous design? A. T0 = 1, T1 = Q2'Q0, T2 = Q2Q0 + Q1Q0 B. T0 = Q0, T1 = Q2Q0, T2 = Q1Q0 C. T0 = 1, T1 = Q0, T2 = Q1Q0 D. T0 = 1, T1 = Q2Q0, T2 = Q2'Q1Q0 Answer: A. T1 must be disabled at count 5 (Q2 = 1) so it uses Q2', and T2 toggles at 3 and 5, giving Q2Q0 + Q1Q0. (Key point: Final T equations) 4. What happens if the MOD-6 counter powers up in the unused state 110? A. It stays in 110 forever B. It goes 110 -> 111 -> 010 and joins the valid sequence C. It goes to 000 immediately D. It goes to 101 Answer: B. The equations drive 110 to 111 and then 111 to 010, a valid state, so the counter is self-starting. (Key point: Unused states and self-start) ## Close variants set in other exams - [Sync vs async; MOD-10 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod10-synchronous-counter) — Digital Logic, chapter 8, asked 2× - [Mod-5 synchronous up counter using SR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-sr) — Digital Logic, chapter 8, asked 5× ## Related in Digital Logic - [Synchronous MOD-5 counter; counter applications](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-sync-applications) — Digital Logic, chapter 8 - [Sync vs async; mod-12 synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod12-synchronous-counter) — Digital Logic, chapter 8, asked 3× - [Mod-6 synchronous up counter using T](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-synchronous-t) — Digital Logic, chapter 8, asked 4× - [Synchronous decade counter with timing](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asynchronous-decade-counter) — Digital Logic, chapter 8, asked 2× - [Mod-5 synchronous counter using JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod5-synchronous-jk) — Digital Logic, chapter 8, asked 4× - [MOD-6 synchronous counter, negative edge JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amod6-sync-jk-negative-edge) — Digital Logic, chapter 8, asked 4× ## Related in other subjects - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Timing diagram of LDA 2080H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lda-2080h) — Microprocessor, chapter 2, asked 2× - [Timing diagram of LXI D, 2465H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lxi-d-2465h) — Microprocessor, chapter 2, asked 2×