--- title: "D flip-flop with excitation table" subject: "Digital Logic" chapter: 6 key: "semester_3/digital_logic:d-flipflop-excitation" source: https://www.bctengineer.com/q/semester_3/digital_logic/d-flipflop-excitation site: BCT Engineering --- # D flip-flop with excitation table Digital Logic · Chapter 6: Flip Flops - Asked in: 2079 Bhadra, 6 marks - Video: [D Flip-Flop Explained | Truth Table and Excitation Table of D Flip-Flop](https://www.youtube.com/watch?v=EILb-DrYr8A) — ALL ABOUT ELECTRONICS - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/d-flipflop-excitation - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6 ## Question Explain the operation of D flip-flop with necessary diagrams truth tables and make its excitation table. ## Short answer The D flip-flop samples D at the active clock edge, so Q+ = D. It uses an SR latch with S = D and R = D' via an inverter, preventing S=R=1. Its excitation table: for Q→0, D=0; 0→1, D=1; 1→0, D=0; 1→1, D=1. ## Answer A **D (data/delay) flip-flop** has a single input D. At the active clock edge, Q takes the value of D and holds it until the next active edge. It is formed from a clocked S-R flip-flop by feeding D to S and D' to R. #### Logic diagram ```text D --+------------>+------+ S* +------+ | | NAND |----->| NAND |---> Q | CLK --+-->| G1 | Q'->| G3 | | | +------+ +------+ | | +------+ R* +------+ | +-->| NAND |----->| NAND |---> Q' +--[NOT]----->| G2 | Q-->| G4 | +------+ +------+ S = D and R = D' : the forbidden S=R=1 never occurs ``` #### Symbol ```text +---------+ D ---| D Q |--- Q CLK -|> | | Q' |--- Q' +---------+ ``` #### Operation 1. **No active clock:** G1 and G2 outputs are 1, so the NAND latch (G3, G4) keeps the old state. 2. **D = 1 at the clock:** S = 1, R = 0. G1 gives S* = 0, which sets the latch: Q = 1, Q' = 0. 3. **D = 0 at the clock:** S = 0, R = 1. G2 gives R* = 0, which resets the latch: Q = 0, Q' = 1. 4. The inverter guarantees $S \neq R$, so the invalid S = R = 1 condition of the S-R flip-flop is removed. #### Truth (characteristic) table | CLK | D | Q+ | Action | |---|---|---|---| | no edge | x | Q | No change | | edge | 0 | 0 | Reset | | edge | 1 | 1 | Set | | D | Q | Q+ | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 1 | Characteristic equation: $Q_{n+1} = D$. #### Excitation table To produce a required change $Q \to Q_{n+1}$, D must simply equal the next state: | Q | Q+ | D | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 0 | | 1 | 1 | 1 | #### Timing diagram (positive edge triggered, Q initially 0) ```text 1 2 3 4 5 6 7 CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾| D ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾| Q _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾ ``` Q follows D only at rising edges, so Q is D delayed by up to one clock period. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With D = 1 at the clock, what happens in the NAND-based D flip-flop? A. S = 0, R = 1 and Q resets B. S = 1, R = 0, G1 output goes 0 and sets Q = 1 C. S = R = 1 D. The latch holds Answer: B. S = D = 1, R = D' = 0, so G1 gives S* = 0 which sets the latch. (Key point: Operation D=1) 2. What does the inverter between D and R guarantee? A. Faster switching B. S and R are never equal, so the invalid S = R = 1 cannot occur C. Q is always 1 D. The clock is inverted Answer: B. Because R = S', the forbidden input is removed. (Key point: Role of inverter) 3. What D is needed for a required change Q to Q+? A. D = Q B. D = Q' C. D = Q+ (the next state) D. D = Q xor Q+ Answer: C. D simply equals the desired next state. (Key point: Excitation table) 4. In the timing diagram, when does Q follow D? A. Continuously B. Only at rising clock edges C. Only when D = 0 D. At falling edges only Answer: B. The flip-flop is positive edge triggered, so Q copies D at rising edges and ignores changes between. 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