---
title: "D to JK and JK to D conversion"
subject: "Digital Logic"
chapter: 6
key: "semester_3/digital_logic:d-to-jk-jk-to-d"
source: https://www.bctengineer.com/q/semester_3/digital_logic/d-to-jk-jk-to-d
site: BCT Engineering
---

# D to JK and JK to D conversion

Digital Logic · Chapter 6: Flip Flops

- Asked in: 2079 Baisakh, 4+2 marks
- Video: [5 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion](https://www.youtube.com/watch?v=ApJ972OYyXQ) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/d-to-jk-jk-to-d
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-6

## Question

Convert D flip-flop into JK flip-flop and JK flip-flop into D flip-flop.

## Short answer

To convert a D flip-flop to JK, derive D = J Q_n' + K' Q_n using excitation tables and K-map, and feed this to D. To convert a JK flip-flop to D, set J = D and K = D' (D inverted) based on the excitation table, so D=1 sets and D=0 resets.

## Answer

#### D flip-flop into JK flip-flop

Find D (the input of the available flip-flop) for each J, K, $Q_n$. D excitation: $D = Q_{n+1}$.

| J | K | $Q_n$ | $Q_{n+1}$ | D |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |

```text
        KQn=00 01 11 10
J=0        0   1  0  0
J=1        1   1  0  1
```

$$
D = J\,Q_n' + K'\,Q_n
$$

```text
J --[AND]--+
Q'--[   ]  +--[OR]-- D +--------+--- Q
K'--[AND]--+           | D FF   |
Q --[   ]              |  CLK   |--- Q'
                       +--------+
```

#### JK flip-flop into D flip-flop

Find J, K for each D, $Q_n$, using the JK excitation table.

| D | $Q_n$ | $Q_{n+1}$ | J | K |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | X |
| 0 | 1 | 0 | X | 1 |
| 1 | 0 | 1 | 1 | X |
| 1 | 1 | 1 | X | 0 |

From the table (using don't cares): $J = D$, $K = D'$.

```text
D --+------------ J +--------+--- Q
    |               | JK FF  |
    +--[NOT]----- K |  CLK   |--- Q'
                    +--------+
```

So D goes to J directly and through an inverter to K. Then $D = 1$ sets and $D = 0$ resets the flip-flop at each clock, which is D flip-flop behaviour.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In converting D to JK, how is D related to the required next state?
   A. D = Qn
   B. D = J K
   C. D = Qn'
   D. D = Qn+1
   Answer: D. The D flip-flop's excitation is simply D = Qn+1. (Key point: D excitation)

2. What is the D input expression to make a JK flip-flop?
   A. D = J Qn' + K' Qn
   B. D = J' Qn + K Qn'
   C. D = J + K
   D. D = J K + Qn
   Answer: A. D = Qn+1 = J Qn' + K' Qn, the JK characteristic equation. (Key point: D for JK)

3. How is a JK flip-flop made into a D flip-flop?
   A. J = 1, K = D
   B. J = D, K = D' (via inverter)
   C. J = D', K = D'
   D. J = K = D
   Answer: B. From the JK excitation table with don't cares, J = D and K = D'. (Key point: JK to D)

4. Why does J = D, K = D' give D-flip-flop action?
   A. D = 1 holds and D = 0 toggles
   B. It makes Q follow the clock
   C. D = 1 sets and D = 0 resets at each clock
   D. D = 1 toggles and D = 0 holds
   Answer: C. J=1,K=0 sets; J=0,K=1 resets, so Q takes D at each clock. (Key point: Behaviour)

## Close variants set in other exams

- [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2×

## Related in Digital Logic

- [Negative edge JK flip-flop; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-negative-edge-t-to-jk) — Digital Logic, chapter 6
- [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2×
- [JK to SR flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-to-sr-conversion) — Digital Logic, chapter 6
- [Flip-flop as state machine; SR to JK](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aflipflop-state-machine-sr-to-jk) — Digital Logic, chapter 6
- [D and T flip-flops; T to JK conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ad-t-flipflops-t-to-jk) — Digital Logic, chapter 6
- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×

## Related in other subjects

- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9
- [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9