---
title: "Decoder; 2-to-4 decoder as a full adder"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:decoder-2to4-full-adder"
source: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-2to4-full-adder
site: BCT Engineering
---

# Decoder; 2-to-4 decoder as a full adder

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2076 Asoj, 1+5 marks
- Video: [Full Adder Implementation using Decoder](https://www.youtube.com/watch?v=u863cwgdlnA) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-2to4-full-adder
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is a decoder? Realize a 2-to-4 line decoder as a full adder circuit.

## Short answer

A decoder converts an n-bit input into 2^n mutually exclusive minterm outputs. For a full adder, feed A and B to a 2-to-4 decoder to obtain D0–D3. Then S = (D1+D2) XOR Cin, and Cout = D3 + (D1+D2)·Cin, using OR, XOR, AND gates.

## Answer

#### Decoder

A **decoder** is a combinational circuit that converts an $n$-bit binary input code into $2^n$ output lines, of which exactly one is active for each input combination. Each output is one minterm of the inputs (e.g. 2-to-4, 3-to-8 (74138), BCD-to-decimal decoders).

#### Full adder using a 2-to-4 decoder

A 2-to-4 decoder has only two inputs, so feed it $A$ and $B$. Its outputs are the minterms of $A, B$:

$$
D_0 = A'B',\quad D_1 = A'B,\quad D_2 = AB',\quad D_3 = AB
$$

Group the full-adder truth table by $AB$ and write $S$ and $C_{out}$ in terms of $C_{in}$:

| AB | Active line | S | $C_{out}$ |
|---|---|---|---|
| 00 | $D_0$ | $C_{in}$ | 0 |
| 01 | $D_1$ | $C_{in}'$ | $C_{in}$ |
| 10 | $D_2$ | $C_{in}'$ | $C_{in}$ |
| 11 | $D_3$ | $C_{in}$ | 1 |

Let $P = D_1 + D_2$ ($= A \oplus B$). Then

$$
\begin{aligned} S &= (D_0 + D_3)C_{in} + (D_1 + D_2)C_{in}' = P \oplus C_{in} \\ C_{out} &= D_3 + (D_1 + D_2)C_{in} = D_3 + P\,C_{in} \end{aligned}
$$

#### Circuit

```text
          +--------+
  A ----->| 2-to-4 |-- D0 (unused)
  B ----->| decoder|-- D1 --+
          |        |-- D2 --+--[OR]-- P
          |        |-- D3 ------------- D3
          +--------+

  P, Cin ---[XOR]--------------------- S
  P, Cin ---[AND]--- P.Cin ---+
  D3 -------------------------+--[OR]-- Cout
```

Gates: 2 OR, 1 XOR, 1 AND.

#### Check

| A B $C_{in}$ | P | S | $C_{out}$ | A+B+C (binary) |
|---|---|---|---|---|
| 0 1 1 | 1 | 0 | 1 | 10 |
| 1 1 0 | 0 | 0 | 1 | 10 |
| 1 1 1 | 0 | 1 | 1 | 11 |
| 1 0 0 | 1 | 1 | 0 | 01 |

All eight combinations were verified.

Alternative: two 2-to-4 decoders with enable can be joined (using $A$ on the enables) into a 3-to-8 decoder; then $S = \Sigma m(1,2,4,7)$ and $C_{out} = \Sigma m(3,5,6,7)$ are taken with two 4-input OR gates.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does an n-to-2^n decoder do?
   A. Selects one of 2^n inputs
   B. Activates exactly one of 2^n outputs for each n-bit input code
   C. Converts 2^n inputs into n bits
   D. Adds two n-bit numbers
   Answer: B. A decoder converts an n-bit code into 2^n lines, one active at a time, each being a minterm. (Key point: Definition of decoder)

2. In the 2-to-4 decoder realization, which signals drive the decoder?
   A. A and Cin
   B. B and Cin
   C. A and B
   D. S and Cout
   Answer: C. A and B go to the decoder; Cin is combined outside with the decoder outputs. (Key point: Decoder inputs)

3. What is P = D1 + D2 equal to?
   A. A AND B
   B. A XOR B
   C. A XNOR B
   D. A OR B
   Answer: B. D1 and D2 are the lines for AB = 01 and 10, so P = A ⊕ B. (Key point: Combined line P)

4. Which equations give the outputs?
   A. S = P AND Cin, Cout = D3 + P XOR Cin
   B. S = P XOR Cin, Cout = D3 + P Cin
   C. S = D3 XOR Cin, Cout = P + Cin
   D. S = P + Cin, Cout = D0 + P Cin
   Answer: B. S = P ⊕ Cin and Cout = D3 + P·Cin, using 2 OR, 1 XOR and 1 AND gate. (Key point: Output equations)

## Related in Digital Logic

- [Full adder using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-2x4-decoder) — Digital Logic, chapter 4, asked 2×
- [Full adder using decoder; (57−43) by 2's complement](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-decoder-subtract) — Digital Logic, chapter 4
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4
- [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×
- [Full adder using a single 4:1 MUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-single-4to1-mux) — Digital Logic, chapter 4

## Related in other subjects

- [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9
- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9