---
title: "Decoder; 3×8 decoder from two 2×4 decoders"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:decoder-3x8-from-2x4"
source: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-3x8-from-2x4
site: BCT Engineering
---

# Decoder; 3×8 decoder from two 2×4 decoders

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2080 Bhadra, 1+4 marks
- Video: [3 to 8 decoder using 2 to 4 decoders](https://www.youtube.com/watch?v=nhO1vobeqBo) — Aasaan padhaai
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-3x8-from-2x4
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

What is meant by a decoder? Construct 3×8 decoder using two 2×4 decoders and additional gates if required.

## Short answer

A decoder converts an n-bit input into one active output among 2^n lines. A 3×8 decoder uses two 2×4 decoders with enable: inputs B and C connect to both decoders; A=0 enables decoder1 (D0–D3), A=1 enables decoder2 (D4–D7), using an inverter on A.

## Answer

A **decoder** is a combinational circuit that converts an $n$-bit binary input code into one of $2^n$ unique output lines; for each input combination exactly one output is active (it generates all minterms).

#### 3×8 decoder using two 2×4 decoders

Let the inputs be $A$ (MSB), $B$, $C$ (LSB). Each 2×4 decoder has an **enable** input $E$ (active high).

- $B$ and $C$ go to the inputs of **both** 2×4 decoders.
- $A$ selects which decoder works: $A'$ (through a NOT gate) drives $E$ of decoder 1 and $A$ drives $E$ of decoder 2.
- When $A = 0$, decoder 1 is enabled and gives $D_0$–$D_3$; when $A = 1$, decoder 2 gives $D_4$–$D_7$.

```text
                 +---------+
B,C --------+--->| 2x4 #1  |--> D0..D3
            |  +>| E       |
            |  | +---------+
            |  |
A --+-[NOT]-|--+
    |       |    +---------+
    |       +--->| 2x4 #2  |--> D4..D7
    +----------->| E       |
                 +---------+
```

| A | B | C | Active output |
|---|---|---|---|
| 0 | 0 | 0 | $D_0$ |
| 0 | 0 | 1 | $D_1$ |
| 0 | 1 | 0 | $D_2$ |
| 0 | 1 | 1 | $D_3$ |
| 1 | 0 | 0 | $D_4$ |
| 1 | 0 | 1 | $D_5$ |
| 1 | 1 | 0 | $D_6$ |
| 1 | 1 | 1 | $D_7$ |

Only one extra gate (an inverter) is needed. With an overall enable $E$, use $E\cdot A'$ and $E\cdot A$ (two AND gates) for the two enables.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does a decoder do?
   A. Converts 2^n lines to an n-bit code
   B. Chooses one of many inputs
   C. Stores binary data
   D. Converts an n-bit code into one of 2^n output lines
   Answer: D. Exactly one output is active for each input combination. (Key point: Decoder definition)

2. In the 3x8 decoder from two 2x4 decoders, what does A do?
   A. It selects which decoder is enabled (A' enables decoder 1 and A enables decoder 2)
   B. It goes to the data inputs of both decoders
   C. It is the LSB of both decoders
   D. It is unused
   Answer: A. B and C go to both decoders; A chooses which one is active. (Key point: Role of A)

3. When A = 1, which outputs can be active?
   A. D0 to D3
   B. D4 to D7
   C. All outputs
   D. D2 to D5
   Answer: B. With A = 1, decoder 2 is enabled and produces D4-D7. (Key point: Outputs)

4. What additional gate is needed in the basic design?
   A. One OR gate
   B. Two XOR gates
   C. One inverter (NOT gate)
   D. None
   Answer: C. A' for decoder 1's enable is the only extra gate. (Key point: Extra hardware)

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