---
title: "5×32 decoder using 3×8 decoders"
subject: "Digital Logic"
chapter: 4
key: "semester_3/digital_logic:decoder-5x32-from-3x8"
source: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-5x32-from-3x8
site: BCT Engineering
---

# 5×32 decoder using 3×8 decoders

Digital Logic · Chapter 4: Data Processing Circuits

- Asked in: 2082 Baisakh, 5 marks; 2081 Baisakh, 5 marks; 2078 Bhadra, 5 marks (asked 3 times)
- Video: [Q. 4.25: Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to- 4](https://www.youtube.com/watch?v=Qcnmb7XuA8Y) — Dr. Dhiman (Learn the art of problem solving) 
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/decoder-5x32-from-3x8
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-4

## Question

Design 5×32 line decoder using 3×8 line decoders and necessary logic gates.

## Short answer

Use four 3×8 decoders. Connect A2A1A0 to all decoder inputs. Decode A4A3 with NOT and AND gates to generate four enable signals, each enabling one decoder. The enabled decoder outputs its 8 lines, yielding 32 outputs.

## Answer

A 5×32 decoder has 5 inputs $A_4A_3A_2A_1A_0$ and 32 outputs $D_0$–$D_{31}$; exactly one output is active for each input code. A 3×8 decoder (e.g. 74138) has 3 inputs, 8 outputs and an enable input E. Since $32/8 = 4$, four 3×8 decoders are needed.

#### Design idea

- The three low bits $A_2A_1A_0$ go to the inputs of **all four** decoders in parallel.
- The two high bits $A_4A_3$ select **which one** decoder is enabled. This is done with two NOT gates and four AND gates (a 2×4 decoding of $A_4A_3$):

| $A_4$ | $A_3$ | Enable signal | Decoder enabled | Outputs active |
|---|---|---|---|---|
| 0 | 0 | $E_0 = \overline{A_4}\,\overline{A_3}$ | DEC 0 | $D_0$–$D_7$ |
| 0 | 1 | $E_1 = \overline{A_4}A_3$ | DEC 1 | $D_8$–$D_{15}$ |
| 1 | 0 | $E_2 = A_4\overline{A_3}$ | DEC 2 | $D_{16}$–$D_{23}$ |
| 1 | 1 | $E_3 = A_4A_3$ | DEC 3 | $D_{24}$–$D_{31}$ |

#### Circuit

```text
A4 ──┬────────[NOT]── A4'
A3 ──┼──┬─────[NOT]── A3'
     │  │
  E0 = A4'·A3'  (AND)
  E1 = A4'·A3   (AND)
  E2 = A4 ·A3'  (AND)
  E3 = A4 ·A3   (AND)

A2 A1 A0 (common to all four decoders)
     │
     ├──>+-----------+
     │   | 3x8  DEC0 |── D0 ... D7
     │   +-----------+
     │       E ── E0
     ├──>+-----------+
     │   | 3x8  DEC1 |── D8 ... D15
     │   +-----------+
     │       E ── E1
     ├──>+-----------+
     │   | 3x8  DEC2 |── D16 ... D23
     │   +-----------+
     │       E ── E2
     └──>+-----------+
         | 3x8  DEC3 |── D24 ... D31
         +-----------+
             E ── E3
```

#### Operation

For an input $A_4A_3A_2A_1A_0$, only one enable is 1, so only one decoder works; the others keep all outputs inactive. Inside that decoder, $A_2A_1A_0$ selects one of its 8 outputs. Output number = $8 \times (A_4A_3)_{10} + (A_2A_1A_0)_{10}$.

**Example:** input 10110 (22): $A_4A_3 = 10$ enables DEC2 (outputs 16–23); $A_2A_1A_0 = 110 = 6$ selects its output 6, i.e. $D_{16+6} = D_{22}$.

(With 74138 chips, the enable can instead be done using its three enable pins $G_1, \overline{G_{2A}}, \overline{G_{2B}}$, but the AND-gate method above works with any 3×8 decoder having one active-high enable.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 3×8 decoders are needed for a 5×32 decoder?
   A. 2
   B. 4
   C. 8
   D. 5
   Answer: B. 32 outputs / 8 outputs per decoder = 4 decoders. (Key point: Number of decoders)

2. What do A4 and A3 do in the design?
   A. Connect to the inputs of all four decoders
   B. Choose which decoder is enabled via NOT and AND gates
   C. Select the output inside each decoder
   D. Are left unused
   Answer: B. A4A3 is decoded into four enable signals; A2A1A0 goes to all decoders in parallel. (Key point: Role of high bits)

3. For input 10110 (22), which output is active?
   A. D6 of DEC0
   B. D22 from DEC2, output 6
   C. D22 from DEC3
   D. D16
   Answer: B. A4A3 = 10 enables DEC2 (outputs 16–23); A2A1A0 = 110 = 6 selects D16+6 = D22. (Key point: Output selection example)

## Related in Digital Logic

- [Decoder; 3×8 decoder from two 2×4 decoders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-3x8-from-2x4) — Digital Logic, chapter 4
- [Encoder; 4×16 decoder from 2×4 decoders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aencoder-4x16-decoder) — Digital Logic, chapter 4
- [Universal gates; positive and negative logic](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-positive-logic) — Digital Logic, chapter 2
- [DEMUX vs decoder; 4×16 decoder from 2×4](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adecoder-4x16-from-2x4) — Digital Logic, chapter 4
- [Full subtractor using a 2×4 decoder](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-2x4-decoder) — Digital Logic, chapter 4, asked 4×
- [Full subtractor using decoder; combinational circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-subtractor-decoder-combinational) — Digital Logic, chapter 4

## Related in other subjects

- [Short note: Logic gates](https://www.bctengineer.com/question.md?key=semester_1%2Fbasic_electrical_and_electronics_engineering%3Ashort-note-logic-gates) — Basic Electrical and Electronics Engineering, chapter 3
- [12 km line at 32.5 kV: regulation and capacitor](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3A12km-32-5kv-regulation-capacitor) — Power System Analysis I, chapter 6
- [Use of VHDL; decoder design](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-use-decoder) — Embedded System, chapter 9
- [Design: 230 m head plant, 20 km line](https://www.bctengineer.com/question.md?key=semester_8%2Fpower_plant_design%3Adesign-2070-230m-20km) — Power Plant Design, chapter 4, asked 14×