---
title: "De Morgan; NOR gate from NAND gates"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:demorgan-importance-nor-from-nand"
source: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-importance-nor-from-nand
site: BCT Engineering
---

# De Morgan; NOR gate from NAND gates

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2074 Asoj, 4 marks
- Video: [Implementation of all logic gates with NAND gate | Design with universal gates | digital electronics](https://www.youtube.com/watch?v=4-kCfYGZDtE) — RF Design Basics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-importance-nor-from-nand
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

What is the importance of De-morgan's laws? Show how a two-input NOR gate can be constructed from a two-input NAND gate.

## Short answer

De Morgan's laws ease complementation, convert SOP to NAND-NAND and POS to NOR-NOR, and show gate equivalence. A NOR gate is built from four NANDs: two as inverters for A' and B', one to produce (A'B')' = A+B, and one inverter to yield (A+B)'.

## Answer

#### Importance of De Morgan's laws
De Morgan's laws ($\overline{A+B} = \bar A\bar B$, $\overline{AB} = \bar A + \bar B$) are used to:
- complement Boolean expressions easily;
- convert AND-OR (SOP) circuits to NAND-NAND and OR-AND (POS) circuits to NOR-NOR;
- build every gate from one universal gate (NAND or NOR), reducing chip types and cost;
- show gate equivalences such as NAND = bubbled OR and NOR = bubbled AND.

#### NOR gate from 2-input NAND gates
Required: $Y = \overline{A + B}$. By De Morgan, $A + B = \overline{\bar A \cdot \bar B}$, so:

$$
\begin{aligned} G_1 &= \overline{A \cdot A} = \bar A \\ G_2 &= \overline{B \cdot B} = \bar B \\ G_3 &= \overline{\bar A \cdot \bar B} = A + B \\ Y &= \overline{G_3 \cdot G_3} = \overline{A + B} \end{aligned}
$$

Four NAND gates are needed: two as input inverters, one to make OR, and one as the output inverter.

```text
 A --[NAND G1]-- A' --+
   (inputs tied)      +--[NAND G3]-- A+B --[NAND G4]-- Y
 B --[NAND G2]-- B' --+                  (inputs tied)
```

| A | B | $\bar A$ | $\bar B$ | $A+B$ | Y |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which circuit conversion is a key use of De Morgan's laws?
   A. Converting SOP (AND-OR) circuits to NAND-NAND
   B. Converting flip-flops to latches
   C. Converting binary to Gray code
   D. Converting NAND gates to counters
   Answer: A. De Morgan's laws let AND-OR circuits be rewritten as NAND-NAND and OR-AND as NOR-NOR. (Key point: Use of De Morgan)

2. Which identity is used to make A + B from NAND gates?
   A. A + B = NAND of A and B
   B. A + B = NAND of A' and B'
   C. A + B = NOR of A and B
   D. A + B = AND of A' and B'
   Answer: B. A + B = (A'.B')' by De Morgan, i.e. a NAND whose inputs are A' and B'. (Key point: Key identity for OR)

3. How many 2-input NAND gates are needed to build a NOR gate?
   A. 2
   B. 3
   C. 4
   D. 5
   Answer: C. Two NANDs invert A and B, one makes A+B, and a fourth inverts it to give (A+B)'. (Key point: Gate count)

4. In the NAND-built NOR, what does the final NAND (inputs tied) do?
   A. Inverts A only
   B. Produces A.B
   C. Produces A xor B
   D. Inverts A+B to give (A+B)'
   Answer: D. G3 gives A+B, and the output NAND with tied inputs complements it to form NOR. (Key point: Role of last gate)

## Related in Digital Logic

- [De Morgan's laws; XOR from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-xor-nand) — Digital Logic, chapter 2
- [De Morgan's laws; XNOR using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-nor) — Digital Logic, chapter 2
- [De Morgan's laws; XOR using 3-input NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xor-three-input-nand) — Digital Logic, chapter 2
- [De Morgan; positive NAND equals negative NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-positive-nand-negative-nor) — Digital Logic, chapter 2
- [De Morgan; X-NOR using a universal gate](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-universal-gate) — Digital Logic, chapter 2
- [Prove De Morgan's theorems; XOR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-prove-xor-nand) — Digital Logic, chapter 2, asked 3×

## Related in other subjects

- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6