---
title: "De Morgan's laws; XOR from NAND gates"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:demorgan-importance-xor-nand"
source: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-importance-xor-nand
site: BCT Engineering
---

# De Morgan's laws; XOR from NAND gates

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2081 Baisakh, 2+3 marks
- Video: [Implementation of all logic gates with NAND gate | Design with universal gates | digital electronics](https://www.youtube.com/watch?v=4-kCfYGZDtE) — RF Design Basics
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-importance-xor-nand
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

What is the importance of De-Morgan's laws? Show how a two-input XOR gate can be constructed from a two-input NAND gate with required expressions.

## Short answer

De Morgan's laws allow complementing expressions, converting SOP/POS forms for NAND/NOR realization, and simplifying circuits. A two-input XOR uses four NAND gates: Y = NAND( NAND(A, NAND(A,B)), NAND(B, NAND(A,B)) ).

## Answer

#### Importance of De Morgan's laws
De Morgan's laws, $\overline{A+B} = \bar A \bar B$ and $\overline{AB} = \bar A + \bar B$, are important because:
1. They let us **complement any Boolean expression** (break the bar, change AND ↔ OR).
2. They convert **SOP forms to NAND-NAND** and **POS forms to NOR-NOR** circuits, so any circuit can be built with one type of universal gate, which reduces IC types and cost.
3. They show gate equivalences: NAND = bubbled OR, NOR = bubbled AND; useful for reading and drawing circuits with active-low signals.
4. They help in **simplifying** expressions and in proving positive/negative logic equivalences.

#### XOR from 2-input NAND gates
$Y = A \oplus B = A\bar B + \bar A B$ needs **four 2-input NAND gates**.

$$
\begin{aligned} Y &= A\bar B + \bar A B \\ &= A(\bar A + \bar B) + B(\bar A + \bar B) \quad (\text{since } A\bar A = B\bar B = 0) \\ &= A\,\overline{AB} + B\,\overline{AB} \\ &= \overline{\overline{A\,\overline{AB}} \cdot \overline{B\,\overline{AB}}} \quad (\text{De Morgan}) \end{aligned}
$$

Gates: $G_1 = \overline{AB}$, $G_2 = \overline{A G_1}$, $G_3 = \overline{B G_1}$, $Y = \overline{G_2 G_3}$.

```text
 A --+---------------[NAND G2]--+
     |                 |        |
     +--[NAND G1]--G1--+        +--[NAND G4]-- Y
     |                 |        |
 B --+---------------[NAND G3]--+
```

| A | B | $G_1$ | $G_2$ | $G_3$ | Y |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 0 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. De Morgan lets SOP convert to what?
   A. NOR-NOR
   B. NAND-NAND circuit
   C. XOR-XOR
   D. AND-AND
   Answer: B. POS converts to NOR-NOR. (Key point: Importance)

2. Benefit?
   A. Needs more IC types
   B. Any circuit with one type of universal gate
   C. Larger circuits
   D. Removes gates
   Answer: B. Reduces IC types and cost. (Key point: Universal gate)

3. NOR equals?
   A. Bubbled AND
   B. Bubbled OR
   C. Plain OR
   D. Plain AND
   Answer: A. NOR = A'B'. (Key point: Bubbled)

4. XOR from 2-input NANDs uses?
   A. 2 gates
   B. 3 gates
   C. 5 gates
   D. 4 gates
   Answer: D. G1..G4. (Key point: XOR count)

## Related in Digital Logic

- [De Morgan's laws; XOR using 3-input NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xor-three-input-nand) — Digital Logic, chapter 2
- [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2
- [Prove De Morgan's theorems; XOR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-prove-xor-nand) — Digital Logic, chapter 2, asked 3×
- [De Morgan's laws; XNOR using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-nor) — Digital Logic, chapter 2
- [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2×
- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×

## Related in other subjects

- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6