---
title: "De Morgan's laws; XOR using 3-input NAND"
subject: "Digital Logic"
chapter: 2
key: "semester_3/digital_logic:demorgan-xor-three-input-nand"
source: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-xor-three-input-nand
site: BCT Engineering
---

# De Morgan's laws; XOR using 3-input NAND

Digital Logic · Chapter 2: Digital Logic

- Asked in: 2076 Asoj, 2+3 marks
- Video: [De Morgan's Law in Boolean Algebra Explained (with Solved Examples)](https://www.youtube.com/watch?v=W7YTfLaPWRY) — ALL ABOUT ELECTRONICS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/demorgan-xor-three-input-nand
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-2

## Question

Describe De' Morgan's laws with examples. Construct XOR gate using only 3-inputs NAND gates.

## Short answer

De Morgan's laws: ¬(A+B)=¬A·¬B, ¬(A·B)=¬A+¬B; extended, ¬(A+B+C)=¬A¬B¬C. XOR using four 3-input NAND gates: tie one unused input of each gate to logic 1, then use the standard 4-gate XOR configuration to produce A⊕B.

## Answer

#### De Morgan's laws
**First theorem:** the complement of a sum (OR) of variables equals the product (AND) of their complements.
$$
\overline{A + B} = \bar{A} \cdot \bar{B}
$$

**Second theorem:** the complement of a product (AND) of variables equals the sum (OR) of their complements.
$$
\overline{A \cdot B} = \bar{A} + \bar{B}
$$

In words: "break the bar and change the sign".

**Examples**
- $\overline{A + B + C} = \bar A \bar B \bar C$ and $\overline{ABC} = \bar A + \bar B + \bar C$ (extended to 3 variables).
- $\overline{(A + \bar B)C} = \overline{A + \bar B} + \bar C = \bar A B + \bar C$.
- Check with A = 1, B = 0: $\overline{1 + 0} = 0$ and $\bar 1 \cdot \bar 0 = 0 \cdot 1 = 0$.

#### XOR gate using only 3-input NAND gates
A 3-input NAND gives $\overline{XYZ}$. If one input is tied to logic 1 (HIGH, e.g. +5 V through a resistor), it behaves as a 2-input NAND: $\overline{X \cdot Y \cdot 1} = \overline{XY}$. (Tying the unused input to one of the used inputs also works, since $XX = X$.) So the 4-NAND XOR circuit is built with four 3-input NAND gates:

$$
\begin{aligned} G_1 &= \overline{A \cdot B \cdot 1} = \overline{AB} \\ G_2 &= \overline{A \cdot G_1 \cdot 1} \\ G_3 &= \overline{B \cdot G_1 \cdot 1} \\ Y &= \overline{G_2 \cdot G_3 \cdot 1} = A\bar B + \bar A B = A \oplus B \end{aligned}
$$

```text
 A --+-------------[NAND3 G2]--+
     |               |    1 -->|
     +--[NAND3 G1]---+         +--[NAND3 G4]-- Y
     |   1 -->|      |         |    1 -->|
 B --+-------------[NAND3 G3]--+
                          1 -->|
 (1 --> : third input tied to logic HIGH)
```

| A | B | $G_1$ | $G_2$ | $G_3$ | Y |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 0 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. (A+B+C)' =
   A. A'+B'+C'
   B. A'B'C'
   C. ABC
   D. A+B+C
   Answer: B. First theorem extended. (Key point: De Morgan example)

2. How can a 3-input NAND act as 2-input NAND?
   A. Tie it LOW
   B. Tie the third input HIGH (or to another input)
   C. Leave it open at 0
   D. Tie to output
   Answer: B. X.Y.1 = XY. (Key point: Tied input)

3. How many 3-input NANDs make XOR?
   A. 4
   B. 2
   C. 3
   D. 6
   Answer: A. Same structure as the 4-NAND XOR. (Key point: Gate count)

4. Why not tie the third input LOW?
   A. Output always 0
   B. It doubles speed
   C. It makes XNOR
   D. Output would be always 1
   Answer: D. X.Y.0 = 0 so NAND is 1. (Key point: Tied LOW)

## Related in Digital Logic

- [De Morgan's laws; XOR from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-xor-nand) — Digital Logic, chapter 2
- [De Morgan; NOR gate from NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-importance-nor-from-nand) — Digital Logic, chapter 2
- [3-input XOR using NAND gates only](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Athree-input-xor-nand) — Digital Logic, chapter 2, asked 2×
- [Prove De Morgan's theorems; XOR using NAND](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-prove-xor-nand) — Digital Logic, chapter 2, asked 3×
- [De Morgan's laws; XNOR using NOR gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ademorgan-xnor-nor) — Digital Logic, chapter 2
- [XOR gate using minimum NAND gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Axor-using-nand-only) — Digital Logic, chapter 2, asked 2×

## Related in other subjects

- [X-OR gate using NAND gates only](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Axor-using-nand) — Basic Electronics Engineering, chapter 6