---
title: "Sequence detector 001 using JK flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-001-jk"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-001-jk
site: BCT Engineering
---

# Sequence detector 001 using JK flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2079 Baisakh, 12 marks
- Video: [[COA 40] Sequential circuit design using JK Flip flops (State diagram, excitation tables), KA = BX'](https://www.youtube.com/watch?v=B2-8irZ_JY0) — The Academician
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-001-jk
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that has a single input 'x' and single output 'z'. The machine is required to give high output when it detects the serial sequence of 001 message. Use JK flip-flops only.

## Short answer

Mealy machine with 2 JK flip-flops; states A(00), B(01), C(10); unused 11 don't care. J1 = Q0 x', K1 = x; J0 = Q1' x', K0 = 1; z = Q1 x. Power-on reset required.

## Answer

The machine has a single input x and a single output z; z = 1 when the last three bits received are 0, 0, 1. Only JK flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 3 bits, 3 states are needed, so **2 JK flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 4 states.)

#### Step 1: States
| Present state | Meaning | Next (x=0) | Next (x=1) | z (x=0) | z (x=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | B | A | 0 | 0 |
| B | "0" received | C | A | 0 | 0 |
| C | "00" received | C | A | 0 | 1 |

#### Step 2: State diagram
```text
 Main path (label = x/z):
 A -0/0-> B -0/0-> C -1/1-> A
 Other transitions:
 A -1/0-> A    B -1/0-> A
 C -0/0-> C
```

#### Step 3: State assignment
| State | A | B | C |
|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 |

Code 11 is unused and is treated as a don't care.

#### Step 4: Excitation table
JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

| Q1 Q0 | x | Q1+ Q0+ | J1 | K1 | J0 | K0 | z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 1 | 0 | X | 1 | X | 0 |
| 0 0 | 1 | 0 0 | 0 | X | 0 | X | 0 |
| 0 1 | 0 | 1 0 | 1 | X | X | 1 | 0 |
| 0 1 | 1 | 0 0 | 0 | X | X | 1 | 0 |
| 1 0 | 0 | 1 0 | X | 0 | 0 | X | 0 |
| 1 0 | 1 | 0 0 | X | 1 | 0 | X | 1 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0x$)
| J1: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | X | X | X | X |

| K1: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 0 | 1 | X | X |

| J0: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 1 | 0 | X | X |
| 1 | 0 | 0 | X | X |

| K0: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 1 | 1 |
| 1 | X | X | X | X |

| z: Q1 / Q0x | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | X | X |

#### Step 6: Equations
$$
\begin{aligned} &J_1 = Q_0\overline{x},\quad K_1 = x \\ &J_0 = \overline{Q_1}\overline{x},\quad K_0 = 1 \\ &z = Q_1x \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1
   | FF0 |       | FF1 |
K0>|K    |    K1>|K    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
x = serial input, common to the gates
J1 = Q0.x'   K1 = x
J0 = Q1'.x'   K0 = 1
z = Q1.x
```
The gates for each flip-flop input are built from the equations; the output gate gives z directly (Mealy output).

**Unused state 11:** with the equations above, from 11 the machine goes to 10 when x = 0 and to 00 when x = 1, so it enters the valid states after one clock. Since z can be 1 from state 11 for one clock, the flip-flops should be cleared to 00 at power-on (reset).

#### Check with an input stream
| x | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | B | C | A | B | C | A | B | C | C |
| z | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |

z = 1 appears exactly on the clock in which the last bit of 001 arrives; overlapping sequences are also detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In state C ("00" received), what happens on x = 0?
   A. Go to A
   B. Go to B
   C. Stay in C, because 000 still ends in 00
   D. Go to C with z = 1
   Answer: C. After 000 the last two bits are still 00, so the machine stays in C with z = 0. (Key point: Overlap in state C)

2. In which condition is z = 1?
   A. State C with x = 0
   B. State B with x = 1
   C. State A with x = 0
   D. State C with x = 1
   Answer: D. 001 is completed when 00 has been received and a 1 arrives, so z = Q1 x (state C, x = 1). The next state is A. (Key point: Detection)

3. Why are the flip-flops cleared to 00 at power-on?
   A. JK flip-flops need a reset input to toggle
   B. From the unused state 11, z could be 1 for one clock
   C. Because state A has code 11
   D. Because K0 = 1 must be removed
   Answer: B. Since 11 is a don't care, z = Q1 x can be 1 in state 11 with x = 1. Clearing to 00 avoids a false output. (Key point: Unused state 11)

4. Why is K0 = 1 and J0 = Q1' x'?
   A. Q0 is 1 only in state B, reached from A with x = 0, otherwise it must be 0
   B. Q0 must always stay 1
   C. Q0 must toggle on every clock
   D. Q0 equals x
   Answer: A. State B (Q0 = 1) is reached only from A with x = 0. So J0 = Q1' x' sets it then, and K0 = 1 clears it otherwise. (Key point: FF0 equations)

## Close variants set in other exams

- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 101 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-jk) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×