---
title: "Sequence detector 011 using RS flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-011-rs"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-011-rs
site: BCT Engineering
---

# Sequence detector 011 using RS flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2075 Chaitra, 11 marks
- Video: [Sequence Detector (Example)](https://www.youtube.com/watch?v=HXG_YPVNIsM) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-011-rs
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a synchronous sequential machine such that it gives output Z=1 if input contains the sequence of message 011 and it retains in its own state in other condition giving output zero. Use RS-Flip-Flop.

## Short answer

Use a Mealy machine with states A(00), B(01), C(10). Z=1 only when 011 completed (C with input 1). S1=Q0 X, R1=Q0', S0=X', R0=X, Z=Q1 X. Two S-R flip-flops.

## Answer

The machine stays in its own state when the input does not advance the sequence (A on 1, B on 0), and gives Z = 0 except when 011 is completed.

A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **011** arrives. Flip-flops: **S-R**.

States (what has been received so far):

- **A**: reset, or last bit 1 not part of a sequence (stays in A on 1)
- **B**: "0" received (stays in B on further 0s)
- **C**: "01" received

#### State diagram (Mealy)

```text
Arc label = input/output

 A --0/0--> B --1/0--> C --1/1--> A

 A --1/0--> A  (self loop)
 B --0/0--> B  (self loop)
 C --0/0--> B
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| A | B | A | 0 | 0 |
| B | B | C | 0 | 0 |
| C | B | A | 0 | 1 |

#### State assignment

A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state).

#### Excitation table of S-R flip-flop

| Q | Q+ | S | R |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 1 | 0 | x | 1 | 0 | 0 |
| 0 0 | 1 | 0 0 | 0 | x | 0 | x | 0 |
| 0 1 | 0 | 0 1 | 0 | x | x | 0 | 0 |
| 0 1 | 1 | 1 0 | 1 | 0 | 0 | 1 | 0 |
| 1 0 | 0 | 0 1 | 0 | 1 | 1 | 0 | 0 |
| 1 0 | 1 | 0 0 | 0 | 1 | 0 | x | 1 |

#### K-maps and simplified equations

```text
S1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    1
Q1Q0=11       x    x
Q1Q0=10       0    0

R1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       x    0
Q1Q0=11       x    x
Q1Q0=10       1    1

S0          X=0  X=1
Q1Q0=00       1    0
Q1Q0=01       x    0
Q1Q0=11       x    x
Q1Q0=10       1    0

R0          X=0  X=1
Q1Q0=00       0    x
Q1Q0=01       0    1
Q1Q0=11       x    x
Q1Q0=10       0    x

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       0    1
```

$$
\begin{aligned} S_1 &= Q_0 X \\ R_1 &= Q_0' \\ S_0 &= X' \\ R_0 &= X \\ Z &= Q_1 X \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $S_1$: a 2-input AND for $Q_0 X$.
- $R_1$: direct line $Q_0'$.
- $S_0$: direct line $X'$.
- $R_0$: direct line $X$.
- $Z$: a 2-input AND for $Q_1 X$.

**Check:** input X = 1011011 gives Z = 0001001; Z = 1 at bits 4 and 7.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which transitions keep the machine in its own state without output?
   A. A on 0 and B on 1
   B. A on 1 and B on 0
   C. C on 1 and A on 0
   D. All states on 1
   Answer: B. Extra 1s while no 0 has been seen keep A, and extra 0s keep B (the last 0 may start 011). (Key point: Staying in own state)

2. In state C ("01") with X = 1, what happens?
   A. Z = 1 and next state A
   B. Z = 0 and next state A
   C. Z = 1 and next state B
   D. Z = 1 and next state C
   Answer: A. 01 plus 1 completes 011, so Z = 1. The last 1 gives no useful tail, so the machine returns to A. (Key point: Detection)

3. How is the unused code 11 treated?
   A. As state C
   B. As don't care (x) in the K-maps, with flip-flops cleared to 00 at start
   C. As a second reset state with Z = 1
   D. It is removed by using three flip-flops
   Answer: B. Three states use codes 00, 01, 10. The code 11 never occurs, so its K-map entries are don't cares. (Key point: Unused code)

4. For a 1 to 0 transition, which S and R are used?
   A. S = 1, R = 0
   B. S = x, R = 0
   C. S = 0, R = 1
   D. S = 0, R = x
   Answer: C. To reset an S-R flip-flop S = 0 and R = 1. (Key point: S-R excitation)

## Related in Digital Logic

- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-t) — Digital Logic, chapter 9
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
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- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
