--- title: "Sequence detector 011 using T flip-flops" subject: "Digital Logic" chapter: 9 key: "semester_3/digital_logic:detector-011-t" source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-011-t site: BCT Engineering --- # Sequence detector 011 using T flip-flops Digital Logic · Chapter 9: Sequential Machines - Asked in: 2080 Bhadra, 10 marks - Video: [Sequence or Pattern Detector](https://www.youtube.com/watch?v=XNAK-L7NlOM) — Neso Academy - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-011-t - Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9 ## Question A asynchronous state machine has one bit serial input. The Y of the machine is set to be high when the input contains the message 011. Draw the state diagram for this machine and design the circuit. Use T Flip-Flop. ## Short answer Three states A(00), B(01), C(10) detect overlapping 011. T flip-flop inputs: T1 = Q1 + Q0 X, T0 = Q0 X + Q0' X', output Z = Q1 X. ## Answer Since flip-flops and a clock are used, the machine is designed as a clocked (synchronous) Mealy machine; the output Y of the question is written Z (Y = Z). A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **011** arrives. Flip-flops: **T**. States (what has been received so far): - **A**: reset / no useful bits (a 1 that does not follow "0", or a completed 011) - **B**: "0" received - **C**: "01" received #### State diagram (Mealy) ```text Arc label = input/output A --0/0--> B --1/0--> C --1/1--> A A --1/0--> A (self loop) B --0/0--> B (self loop) C --0/0--> B ``` #### State table | Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) | |---|---|---|---|---| | A | B | A | 0 | 0 | | B | B | C | 0 | 0 | | C | B | A | 0 | 1 | #### State assignment A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to B, X=1 goes to A), so it is self-starting. #### Excitation table of T flip-flop | Q | Q+ | T | |---|---|---| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | #### Transition and excitation table | Q1 Q0 | X | Q1+ Q0+ | T1 | T0 | Z | |---|---|---|---|---|---| | 0 0 | 0 | 0 1 | 0 | 1 | 0 | | 0 0 | 1 | 0 0 | 0 | 0 | 0 | | 0 1 | 0 | 0 1 | 0 | 0 | 0 | | 0 1 | 1 | 1 0 | 1 | 1 | 0 | | 1 0 | 0 | 0 1 | 1 | 1 | 0 | | 1 0 | 1 | 0 0 | 1 | 0 | 1 | #### K-maps and simplified equations ```text T1 X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 1 Q1Q0=11 x x Q1Q0=10 1 1 T0 X=0 X=1 Q1Q0=00 1 0 Q1Q0=01 0 1 Q1Q0=11 x x Q1Q0=10 1 0 Z X=0 X=1 Q1Q0=00 0 0 Q1Q0=01 0 0 Q1Q0=11 x x Q1Q0=10 0 1 ``` $$ \begin{aligned} T_1 &= Q_0 X + Q_1 \\ T_0 &= Q_0 X + Q_0' X' \\ Z &= Q_1 X \end{aligned} $$ #### Logic diagram ```text +-------------+ +----------+ X ------>| next-state |---->| FF1, FF0 |--+--> Q1, Q0 +----->| logic | | (CLK) | | | +-------------+ +----------+ | +-------------------<--------------------+ | +-------------+ +----->| output |----> Z X ------>| logic | +-------------+ ``` Gates needed (two T flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates): - $T_1$: a 2-input AND for $Q_0 X$; direct line $Q_1$, combined in a 2-input OR gate. - $T_0$: a 2-input AND for $Q_0 X$; a 2-input AND for $Q_0' X'$, combined in a 2-input OR gate. - $Z$: a 2-input AND for $Q_1 X$. **Check:** input X = 0011011 gives Z = 0001001; Z = 1 at bits 4 and 7. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Although the question says asynchronous, why is the machine designed as clocked? A. Flip-flops and a clock are used B. T flip-flops need no clock C. It must be fundamental mode D. Mealy machines are always asynchronous Answer: A. Since flip-flops and a clock are used, it is designed as a clocked Mealy machine. (Key point: Clocked design) 2. Why does C --0/0--> B (not A)? A. C must reset after any 0 B. The 0 can start a new 011, so B (0 received) is correct C. B is the reset state D. The 0 completes a detection Answer: B. After 01 followed by 0, the last bit is 0, which is the first bit of a possible 011. (Key point: State transition) 3. What does B do on X=0 and why? A. Goes to A B. Goes to C C. Stays in B because the last bit is still 0 D. Output becomes 1 Answer: C. Another 0 leaves '0' as the useful tail, so B stays in B. (Key point: State B) 4. Which equation gives Z for 011? A. Z = Q1 X' B. Z = Q0 X C. Z = Q1' Q0 X D. Z = Q1 X Answer: D. Z = 1 only in C (10) with X=1, which simplifies to Q1 X. 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