---
title: "Sequence detector for 100"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-100"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-100
site: BCT Engineering
---

# Sequence detector for 100

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2074 Asoj, 10 marks
- Video: [Sequence Detector (Example)](https://www.youtube.com/watch?v=HXG_YPVNIsM) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-100
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that produces output Y = 1 when it detects the serial input X = 100.

## Short answer

Use a Mealy machine with states A(00), B(01), C(10). Z=1 when 100 detected (C with X=0). J1=Q0 X', K1=1, J0=X, K0=X', Z=Q1 X'. Two J-K flip-flops.

## Answer

No flip-flop type is specified, so J-K flip-flops are used (output named Y in the question is written Z below; Y = Z).

A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **100** arrives. Flip-flops: **J-K**.

States (what has been received so far):

- **A**: reset / no useful bits
- **B**: "1" received
- **C**: "10" received

#### State diagram (Mealy)

```text
Arc label = input/output

 A --1/0--> B --0/0--> C --0/1--> A

 A --0/0--> A  (self loop)
 B --1/0--> B  (self loop)
 C --1/0--> B
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| A | A | B | 0 | 0 |
| B | C | B | 0 | 0 |
| C | A | B | 1 | 0 |

#### State assignment

A = 00, B = 01, C = 10 (flip-flop outputs $Q_1 Q_0$). The unused code 11 is taken as don't care (x) in all K-maps. The flip-flops are cleared to 00 at power-on (start state). Checking the final equations, from 11 the machine goes to a valid state on the next clock (X=0 goes to A, X=1 goes to B), so it is self-starting.

#### Excitation table of J-K flip-flop

| Q | Q+ | J | K |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | x |
| 1 | 0 | x | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | x | 0 | x | 0 |
| 0 0 | 1 | 0 1 | 0 | x | 1 | x | 0 |
| 0 1 | 0 | 1 0 | 1 | x | x | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | x | x | 0 | 0 |
| 1 0 | 0 | 0 0 | x | 1 | 0 | x | 1 |
| 1 0 | 1 | 0 1 | x | 1 | 1 | x | 0 |

#### K-maps and simplified equations

```text
J1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       1    0
Q1Q0=11       x    x
Q1Q0=10       x    x

K1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       x    x
Q1Q0=11       x    x
Q1Q0=10       1    1

J0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       x    x
Q1Q0=11       x    x
Q1Q0=10       0    1

K0          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       1    0
Q1Q0=11       x    x
Q1Q0=10       x    x

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       x    x
Q1Q0=10       1    0
```

$$
\begin{aligned} J_1 &= Q_0 X' \\ K_1 &= 1 \\ J_0 &= X \\ K_0 &= X' \\ Z &= Q_1 X' \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two J-K flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $J_1$: a 2-input AND for $Q_0 X'$.
- $K_1$: tied to logic 1.
- $J_0$: direct line $X$.
- $K_0$: direct line $X'$.
- $Z$: a 2-input AND for $Q_1 X'$.

**Check:** input X = 1100100 gives Z = 0001001; Z = 1 at bits 4 and 7.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In state C ("10" received), what happens on X = 0?
   A. Z = 0, next state B
   B. Z = 1, next state B
   C. Z = 1, next state A
   D. Z = 0, next state A
   Answer: C. 10 plus 0 completes 100, so Z = 1. The trailing 0 has no useful tail, so the machine returns to A. (Key point: Detection)

2. In state C with X = 1, the next state is B. Why?
   A. The sequence is lost and the machine must reset to A
   B. 101 ends with a 1, which may start a new 100
   C. The machine counts the 1s
   D. It detects 101
   Answer: B. 101 does not match 100, but its last 1 is a possible start of a new 100, so the next state is B. (Key point: Overlap in state C)

3. What is Z?
   A. Z = Q1' Q0 X'
   B. Z = Q1 X
   C. Z = Q1 Q0 X'
   D. Z = Q1 X'
   Answer: D. Z = 1 only in state C (Q1 = 1, 11 is a don't care) when X = 0, so Z = Q1 X'. (Key point: Output equation)

4. Why is K1 = 1?
   A. Q1 is 1 only in state C, and every transition from C leaves it (to A or B)
   B. Q1 must always toggle
   C. Q1 stays 1 in all states
   D. K1 = X for all states
   Answer: A. From C, both inputs go to a state with Q1 = 0, so whenever Q1 = 1 it must be reset: K1 = 1. (Key point: K1 equation)

## Related in Digital Logic

- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×

## Related in other subjects

- [Sequence detector 1101 FSM and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1101) — Embedded System, chapter 9
- [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7
- [Sequence detector 1011 state diagram and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1011) — Embedded System, chapter 9
- [Output for sinusoid mix input, h=(1/2)^n u[n]](https://www.bctengineer.com/question.md?key=semester_7%2Fdigital_signal_analysis_and_processing%3Alti-output-sinusoid-mix) — Digital Signal Analysis and Processing, chapter 3