---
title: "Sequence detector 1001 using SR flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1001-sr"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1001-sr
site: BCT Engineering
---

# Sequence detector 1001 using SR flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2078 Bhadra, 10 marks
- Video: [Sequence or Pattern Detector](https://www.youtube.com/watch?v=XNAK-L7NlOM) — Neso Academy
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1001-sr
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that has one serial input X and one output Z. The machine is required to give an output z = 1 when the input X contains the message 1001. Use S-R flip-flop.

## Short answer

Mealy machine with 2 S-R flip-flops; states A(00), B(01), C(10), D(11). S1 = Q1' Q0 X', R1 = Q1 Q0 + X; S0 = Q1 Q0' + X, R0 = Q0 X'; Z = Q1 Q0 X.

## Answer

The machine has one serial input X and one output Z; Z = 1 in the clock period in which the last bit of **1001** arrives. **S-R** flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the input), so fewer states are needed. Overlapping sequences are allowed: after a detection, the machine keeps the useful tail of the input.

States (what has been received so far):

- **A**: reset / no useful bits
- **B**: "1" received
- **C**: "10" received
- **D**: "100" received

#### State diagram (Mealy)

```text
Arc label = input/output

 A --1/0--> B --0/0--> C --0/0--> D --1/1--> B

 A --0/0--> A  (self loop)
 B --1/0--> B  (self loop)
 C --1/0--> B
 D --0/0--> A
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| A | A | B | 0 | 0 |
| B | C | B | 0 | 0 |
| C | D | B | 0 | 0 |
| D | A | B | 0 | 1 |

#### State assignment

A = 00, B = 01, C = 10, D = 11 (flip-flop outputs $Q_1 Q_0$).

#### Excitation table of S-R flip-flop

(x = don't care)

| Q | Q+ | S | R |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | S1 | R1 | S0 | R0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | x | 0 | x | 0 |
| 0 0 | 1 | 0 1 | 0 | x | 1 | 0 | 0 |
| 0 1 | 0 | 1 0 | 1 | 0 | 0 | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | x | x | 0 | 0 |
| 1 0 | 0 | 1 1 | x | 0 | 1 | 0 | 0 |
| 1 0 | 1 | 0 1 | 0 | 1 | 1 | 0 | 0 |
| 1 1 | 0 | 0 0 | 0 | 1 | 0 | 1 | 0 |
| 1 1 | 1 | 0 1 | 0 | 1 | x | 0 | 1 |

#### K-maps and simplified equations

```text
S1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       1    0
Q1Q0=11       0    0
Q1Q0=10       x    0

R1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       0    x
Q1Q0=11       1    1
Q1Q0=10       0    1

S0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       0    x
Q1Q0=11       0    x
Q1Q0=10       1    1

R0          X=0  X=1
Q1Q0=00       x    0
Q1Q0=01       1    0
Q1Q0=11       1    0
Q1Q0=10       0    0

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       0    1
Q1Q0=10       0    0
```

$$
\begin{aligned} S_1 &= Q_1' Q_0 X' \\ R_1 &= Q_1 Q_0 + X \\ S_0 &= Q_1 Q_0' + X \\ R_0 &= Q_0 X' \\ Z &= Q_1 Q_0 X \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two S-R flip-flops with a common clock; complements are taken from the $Q'$ outputs or from NOT gates):

- $S_1$: a 3-input AND for $Q_1' Q_0 X'$.
- $R_1$: a 2-input AND for $Q_1 Q_0$, combined with the direct line $X$ in a 2-input OR gate.
- $S_0$: a 2-input AND for $Q_1 Q_0'$, combined with the direct line $X$ in a 2-input OR gate.
- $R_0$: a 2-input AND for $Q_0 X'$.
- $Z$: a 3-input AND for $Q_1 Q_0 X$.

**Check:** input X = 01001001 gives Z = 00001001; Z = 1 at the 5th and 8th bits, so both overlapping 1001s are detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For a transition 0 to 1 in an S-R flip-flop, what are S and R?
   A. S = 0, R = 1
   B. S = 1, R = 0
   C. S = 1, R = 1
   D. S = x, R = 0
   Answer: B. To set the flip-flop, S = 1 and R = 0. For 1 to 0 it is S = 0, R = 1. (Key point: S-R excitation)

2. In state D ("100") with X = 0, what is the next state?
   A. C
   B. D
   C. B
   D. A, since 1000 has no useful tail
   Answer: D. 1000 ends in 0s with no prefix of 1001 as a tail, so the machine returns to A. (Key point: Overlap in state D)

3. The input 01001001 gives Z = 00001001. Why does Z = 1 appear twice?
   A. The machine resets after each detection
   B. Overlapping is allowed: after detection the useful tail 1 is kept (D to B on 1)
   C. The Moore output is delayed one clock
   D. Two flip-flops store two sequences
   Answer: B. The 1 that ends the first 1001 also starts the next one, and the machine keeps it by going to B. (Key point: Output and overlap)

4. What is Z?
   A. Z = Q1' Q0 X
   B. Z = Q1 Q0' X
   C. Z = Q1 Q0 X
   D. Z = Q1 Q0 X'
   Answer: C. Z = 1 in state D (11) when X = 1. (Key point: Output equation)

## Close variants set in other exams

- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector for 110](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110) — Digital Logic, chapter 9, asked 5×
- [Sequence detector for 1010](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010) — Digital Logic, chapter 9, asked 5×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-sr-msb) — Digital Logic, chapter 9
- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [SR flip-flop operation](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Asr-flip-flop) — Basic Electronics Engineering, chapter 6, asked 6×
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×