---
title: "Sequence detector 101 using JK flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-101-jk"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-101-jk
site: BCT Engineering
---

# Sequence detector 101 using JK flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2075 Chaitra, 10 marks; 2073 Shrawan, 12 marks (asked 2 times)
- Video: [Moore and mealy sequential detector 101 part1](https://www.youtube.com/watch?v=RoSY__82gdg) — Eng Ahmed Shouman
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-101-jk
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that detects 101 from input stream X by making Y is 1. Using J-K flip-flop.

## Short answer

Implement as an overlapping Mealy machine with two JK flip-flops and three states (unused 11). State A=00, B=01, C=10. Equations: J1 = Q0 X', K1 = 1; J0 = X, K0 = X'; output Y = Q1 X. Initialize to 00.

## Answer

The machine watches the serial input X and makes Y = 1 when the last three bits received are 1, 0, 1.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 3 bits, 3 states are needed, so **2 JK flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 4 states.)

#### Step 1: States
| Present state | Meaning | Next (X=0) | Next (X=1) | Y (X=0) | Y (X=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | C | B | 0 | 0 |
| C | "10" received | A | B | 0 | 1 |

#### Step 2: State diagram
```text
 Main path (label = X/Y):
 A -1/0-> B -0/0-> C -1/1-> B
 Other transitions:
 A -0/0-> A    B -1/0-> B
 C -0/0-> A
```

#### Step 3: State assignment
| State | A | B | C |
|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 |

Code 11 is unused and is treated as a don't care.

#### Step 4: Excitation table
JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

| Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Y |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | X | 0 | X | 0 |
| 0 0 | 1 | 0 1 | 0 | X | 1 | X | 0 |
| 0 1 | 0 | 1 0 | 1 | X | X | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | X | X | 0 | 0 |
| 1 0 | 0 | 0 0 | X | 1 | 0 | X | 0 |
| 1 0 | 1 | 0 1 | X | 1 | 1 | X | 1 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0X$)
| J1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | X | X | X | X |

| K1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | X | X |
| 1 | 1 | 1 | X | X |

| J0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | X | X |
| 1 | 0 | 1 | X | X |

| K0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | X | X | 0 | 1 |
| 1 | X | X | X | X |

| Y: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | X | X |

#### Step 6: Equations
$$
\begin{aligned} &J_1 = Q_0\overline{X},\quad K_1 = 1 \\ &J_0 = X,\quad K_0 = \overline{X} \\ &Y = Q_1X \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1
   | FF0 |       | FF1 |
K0>|K    |    K1>|K    |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
J1 = Q0.X'   K1 = 1
J0 = X   K0 = X'
Y = Q1.X
```
The gates for each flip-flop input are built from the equations; the output gate gives Y directly (Mealy output).

**Unused state 11:** with the equations above, from 11 the machine goes to 00 when X = 0 and to 01 when X = 1, so it enters the valid states after one clock. Since Y can be 1 from state 11 for one clock, the flip-flops should be cleared to 00 at power-on (reset).

#### Check with an input stream
| X | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | A | B | C | B | C | B | B | C | B |
| Y | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |

Y = 1 appears exactly on the clock in which the last bit of 101 arrives; overlapping sequences are also detected.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many states does the Mealy 101 detector need, and how many JK flip-flops?
   A. 4 states, 2 flip-flops
   B. 3 states, 3 flip-flops
   C. 3 states, 2 flip-flops
   D. 2 states, 1 flip-flop
   Answer: C. A 3-bit sequence needs 3 Mealy states (A, B, C), which require 2 flip-flops. Code 11 stays unused. (Key point: States needed)

2. In state C ("10" received), what happens on X = 1?
   A. Go to B with Y = 1
   B. Go to A with Y = 1
   C. Go to A with Y = 0
   D. Stay in C with Y = 0
   Answer: A. 10 followed by 1 completes 101, so Y = 1. The last 1 can start a new sequence, so the next state is B. (Key point: Overlap in state C)

3. Why is the output Y = Q1 X?
   A. Y = 1 in state B whenever X = 0
   B. Y = 1 in state C (Q1Q0 = 10) when X = 1
   C. Y = 1 whenever X = 1
   D. Y = 1 in state A when X = 1
   Answer: B. Only state C with X = 1 completes 101. Since 11 is a don't care, Q1 alone identifies state C. (Key point: Output equation)

4. Why should the flip-flops be cleared at power-on?
   A. JK flip-flops cannot work without a reset
   B. To make J1 equal Q0 X'
   C. To avoid the state 11, where Y could be 1 for one clock
   D. To change the machine into a Moore machine
   Answer: C. Y = Q1 X can be 1 in state 11 with X = 1, giving a false detection. Resetting to 00 avoids this. (Key point: Unused state 11)

## Related in Digital Logic

- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9