---
title: "Sequence detector 1010 using T flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1010-t"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1010-t
site: BCT Engineering
---

# Sequence detector 1010 using T flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2080 Bhadra, 10 marks
- Video: [VLSI : sequence detector 1010 || sequence detector 1011 overlapping mealy FSM](https://www.youtube.com/watch?v=EUosQBSw2qQ) — VLSI-LEARNINGS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1010-t
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine that has one serial input X and one output Z. The machine is required to give an output Z = 1, when the serial input X contains the message 1010. Use T flip-flop.

## Short answer

Mealy machine with 2 T flip-flops; states A(00), B(01), C(10), D(11). T1 = Q1Q0X + Q1Q0'X' + Q1'Q0X', T0 = Q0 xor X, Z = Q1Q0X'. Overlapping sequences detected.

## Answer

The machine has one serial input X and one output Z; Z = 1 when the last four bits received are 1, 0, 1, 0. T flip-flops are used.

A **Mealy** machine is used (output depends on the present state and the present input), and overlapping sequences are detected. Since the sequence has 4 bits, 4 states are needed, so **2 T flip-flops** ($Q_1Q_0$) are used, clocked on the positive edge. (A Moore machine would need 5 states.)

#### Step 1: States
| Present state | Meaning | Next (X=0) | Next (X=1) | Z (X=0) | Z (X=1) |
|---|---|---|---|---|---|
| A | reset / no useful bits | A | B | 0 | 0 |
| B | "1" received | C | B | 0 | 0 |
| C | "10" received | A | D | 0 | 0 |
| D | "101" received | C | B | 1 | 0 |

#### Step 2: State diagram
```text
 Main path (label = X/Z):
 A -1/0-> B -0/0-> C -1/0-> D -0/1-> C
 Other transitions:
 A -0/0-> A    B -1/0-> B
 C -0/0-> A    D -1/0-> B
```

#### Step 3: State assignment
| State | A | B | C | D |
|---|---|---|---|---|
| Q1 Q0 | 0 0 | 0 1 | 1 0 | 1 1 |

#### Step 4: Excitation table
T excitation: T = 1 when the flip-flop must change, T = 0 when it must hold ($T = Q \oplus Q^+$).

| Q1 Q0 | X | Q1+ Q0+ | T1 | T0 | Z |
|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | 0 | 0 |
| 0 0 | 1 | 0 1 | 0 | 1 | 0 |
| 0 1 | 0 | 1 0 | 1 | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | 0 | 0 |
| 1 0 | 0 | 0 0 | 1 | 0 | 0 |
| 1 0 | 1 | 1 1 | 0 | 1 | 0 |
| 1 1 | 0 | 1 0 | 0 | 1 | 1 |
| 1 1 | 1 | 0 1 | 1 | 0 | 0 |

#### Step 5: K-maps (rows $Q_1$, columns $Q_0X$)
| T1: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |

| T0: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 |

| Z: Q1 / Q0X | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 |

#### Step 6: Equations
$$
\begin{aligned} &T_1 = Q_1Q_0X + Q_1\overline{Q_0}\overline{X} + \overline{Q_1}Q_0\overline{X} \\ &T_0 = Q_0\overline{X} + \overline{Q_0}X \\ &Z = Q_1Q_0\overline{X} \end{aligned}
$$

#### Step 7: Logic diagram
```text
   +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1
   | FF0 |       | FF1 |
   |     |       |     |
   +--^--+       +--^--+
      |             |
CLK---+-------------+
X = serial input, common to the gates
T1 = Q1.Q0.X + Q1.Q0'.X' + Q1'.Q0.X'
T0 = Q0.X' + Q0'.X
Z = Q1.Q0.X'
```
The gates for each flip-flop input are built from the equations; the output gate gives Z directly (Mealy output).

#### Check with an input stream
| X | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
|---|---|---|---|---|---|---|---|---|---|---|
| State | A | B | C | D | C | D | C | A | B | C |
| Z | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |

Z = 1 appears exactly on the clock in which the last bit of 1010 arrives; overlapping sequences are also detected.

Note: $T_0 = Q_0 \oplus X$, so FF0 needs only one XOR gate.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which statement about the T flip-flop excitation is correct?
   A. T = 1 when the flip-flop holds, T = 0 when it changes
   B. T = Q xor Q+, so T = 1 means the flip-flop must change
   C. T = Q+ (T equals the next state)
   D. T = 1 only for 0 to 1 transitions
   Answer: B. T toggles the flip-flop, so T = 1 exactly when the state must change: T = Q xor Q+. (Key point: T excitation)

2. In state D ("101"), input X = 0 gives Z = 1. What is the next state?
   A. A
   B. B
   C. D
   D. C, because the tail "10" can start another 1010
   Answer: D. After 1010 the last two bits 10 are a useful start of a new 1010, so the machine goes to C. (Key point: Overlap from state D)

3. Z = 1 for which state and input?
   A. State D (11) with X = 0
   B. State C (10) with X = 1
   C. State D (11) with X = 1
   D. State B (01) with X = 0
   Answer: A. The output is 1 when 101 has been received and the 0 arrives: Z = Q1 Q0 X'. (Key point: Output equation)

## Close variants set in other exams

- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector for 110](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110) — Digital Logic, chapter 9, asked 5×
- [Sequence detector for 1010](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010) — Digital Logic, chapter 9, asked 5×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in Digital Logic

- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1110 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1110-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
- [Sequence detector 1101 FSM and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1101) — Embedded System, chapter 9