---
title: "Sequence detector 1011 using JK flip-flops"
subject: "Digital Logic"
chapter: 9
key: "semester_3/digital_logic:detector-1011-jk"
source: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1011-jk
site: BCT Engineering
---

# Sequence detector 1011 using JK flip-flops

Digital Logic · Chapter 9: Sequential Machines

- Asked in: 2076 Asoj, 12 marks
- Video: [VLSI : sequence detector 1010 || sequence detector 1011 overlapping mealy FSM](https://www.youtube.com/watch?v=EUosQBSw2qQ) — VLSI-LEARNINGS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_3/digital_logic/detector-1011-jk
- Whole chapter: https://www.bctengineer.com/md/semester_3/digital_logic/chapter-9

## Question

Design a sequential machine with one input x and one output z which gives output z=1 when serial input contains 1011 message. Use J-K flip-flop.

## Short answer

Use a Mealy machine with states A(00), B(01), C(10), D(11) for no bits, 1, 10, 101. Overlapping allowed. J1=Q0 X', K1=Q0 X+Q0' X', J0=X, K0=X', Z=Q1 Q0 X. Implement with two J-K flip-flops.

## Answer

A **Mealy** machine is used (output depends on present state and input), so fewer states are needed. Overlapping sequences are allowed: after a detection the machine keeps the useful tail of the input. One input X and one output Z; Z = 1 in the clock period in which the last bit of **1011** arrives. Flip-flops: **J-K**.

States (what has been received so far):

- **A**: reset / no useful bits
- **B**: "1" received
- **C**: "10" received
- **D**: "101" received

#### State diagram (Mealy)

```text
Arc label = input/output

 A --1/0--> B --0/0--> C --1/0--> D --1/1--> B

 A --0/0--> A  (self loop)
 B --1/0--> B  (self loop)
 C --0/0--> A
 D --0/0--> C
```

#### State table

| Present state | Next, X=0 | Next, X=1 | Z (X=0) | Z (X=1) |
|---|---|---|---|---|
| A | A | B | 0 | 0 |
| B | C | B | 0 | 0 |
| C | A | D | 0 | 0 |
| D | C | B | 0 | 1 |

#### State assignment

A = 00, B = 01, C = 10, D = 11 (flip-flop outputs $Q_1 Q_0$). 

#### Excitation table of J-K flip-flop

| Q | Q+ | J | K |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | x |
| 1 | 0 | x | 1 |
| 1 | 1 | x | 0 |

#### Transition and excitation table

| Q1 Q0 | X | Q1+ Q0+ | J1 | K1 | J0 | K0 | Z |
|---|---|---|---|---|---|---|---|
| 0 0 | 0 | 0 0 | 0 | x | 0 | x | 0 |
| 0 0 | 1 | 0 1 | 0 | x | 1 | x | 0 |
| 0 1 | 0 | 1 0 | 1 | x | x | 1 | 0 |
| 0 1 | 1 | 0 1 | 0 | x | x | 0 | 0 |
| 1 0 | 0 | 0 0 | x | 1 | 0 | x | 0 |
| 1 0 | 1 | 1 1 | x | 0 | 1 | x | 0 |
| 1 1 | 0 | 1 0 | x | 0 | x | 1 | 0 |
| 1 1 | 1 | 0 1 | x | 1 | x | 0 | 1 |

#### K-maps and simplified equations

```text
J1          X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       1    0
Q1Q0=11       x    x
Q1Q0=10       x    x

K1          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       x    x
Q1Q0=11       0    1
Q1Q0=10       1    0

J0          X=0  X=1
Q1Q0=00       0    1
Q1Q0=01       x    x
Q1Q0=11       x    x
Q1Q0=10       0    1

K0          X=0  X=1
Q1Q0=00       x    x
Q1Q0=01       1    0
Q1Q0=11       1    0
Q1Q0=10       x    x

Z           X=0  X=1
Q1Q0=00       0    0
Q1Q0=01       0    0
Q1Q0=11       0    1
Q1Q0=10       0    0
```

$$
\begin{aligned} J_1 &= Q_0 X' \\ K_1 &= Q_0 X + Q_0' X' \\ J_0 &= X \\ K_0 &= X' \\ Z &= Q_1 Q_0 X \end{aligned}
$$

#### Logic diagram

```text
           +-------------+     +----------+
 X  ------>| next-state  |---->| FF1, FF0 |--+--> Q1, Q0
    +----->| logic       |     |  (CLK)   |  |
    |      +-------------+     +----------+  |
    +-------------------<--------------------+
    |      +-------------+
    +----->| output      |----> Z
 X  ------>| logic       |
           +-------------+
```

Gates needed (two J-K flip-flops with a common clock; complements are taken from the $Q'$ outputs or NOT gates):

- $J_1$: a 2-input AND for $Q_0 X'$.
- $K_1$: a 2-input AND for $Q_0 X$; a 2-input AND for $Q_0' X'$, combined in a 2-input OR gate.
- $J_0$: direct line $X$.
- $K_0$: direct line $X'$.
- $Z$: a 3-input AND for $Q_1 Q_0 X$.

**Check:** input X = 1011011 gives Z = 0001001; Z = 1 at bits 4 and 7 (overlapping 1011011). From D, input 0 gives "1010" whose useful tail is "10", so D goes to C.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In state D ("101") with X = 0, what is the next state?
   A. A
   B. C, since 1010 ends with the useful tail "10"
   C. B
   D. D
   Answer: B. 101 followed by 0 is 1010, whose tail 10 can start a new 1011, so the next state is C. (Key point: Overlap from state D)

2. When is Z = 1?
   A. State C with X = 1
   B. State D with X = 0
   C. State D with X = 1
   D. State B with X = 1
   Answer: C. 1011 is completed when 101 has been received and a 1 arrives, giving Z = Q1 Q0 X. The next state is B. (Key point: Detection)

3. What are the JK inputs for a transition 1 to 0?
   A. J = 0, K = x
   B. J = x, K = 1
   C. J = x, K = 0
   D. J = 1, K = x
   Answer: B. To reset a flip-flop J is a don't care and K = 1. For 1 to 1: J = x, K = 0. (Key point: JK excitation)

4. The input 1011011 gives Z = 0001001. Why is there a second Z = 1?
   A. The sequence 1011 is repeated from scratch
   B. The machine gets two clock edges
   C. The last 1 of the first 1011 is reused to start the next one (D to B)
   D. State A outputs 1
   Answer: C. After the first detection the machine goes to B ("1"), so 011 completes another 1011 overlapping the first. (Key point: Check of overlap)

## Close variants set in other exams

- [Sequence detector 1010 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1010-t) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-sr) — Digital Logic, chapter 9, asked 7×

## Related in Digital Logic

- [Sequence detector 1011 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1011-t) — Digital Logic, chapter 9, asked 2×
- [Sequence detector 001 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-001-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 011 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-011-jk) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 110 using JK flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-110-jk) — Digital Logic, chapter 9, asked 3×
- [Sequence detector 1101 using SR flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1101-sr) — Digital Logic, chapter 9, asked 7×
- [Sequence detector 1001 using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-1001-d) — Digital Logic, chapter 9, asked 9×

## Related in other subjects

- [Combinational vs sequential; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Acomb-vs-seq-jk) — Basic Electronics Engineering, chapter 6
- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Sequence detector 1011 state diagram and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-sequence-detector-1011) — Embedded System, chapter 9
- [JK flip-flop operation and truth table](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ajk-flip-flop) — Basic Electronics Engineering, chapter 6